^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __PCI_SH4_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __PCI_SH4_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) defined(CONFIG_CPU_SUBTYPE_SH7785) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) defined(CONFIG_CPU_SUBTYPE_SH7763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "pci-sh7780.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "pci-sh7751.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SH4_PCICR 0x100 /* PCI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SH4_PCIINT 0x114 /* PCI Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SH4_PCIALR 0x11C /* Error Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SH4_PCICLR 0x120 /* Error Command/Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SH4_PCICLR_MPIO 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SH4_PCIBMLR 0x138 /* Error Bus Master Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SH4_PCIDCR0 0x18C /* DMA0 Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SH4_PCIDCR1 0x19C /* DMA1 Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SH4_PCIPAR 0x1C0 /* PIO Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SH4_PCIMBR 0x1C4 /* Memory Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* For definitions of BCR, MCR see ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SH4_PCIMBR0 SH4_PCIBCR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SH4_PCIMBMR0 SH4_PCIBCR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SH4_PCIMBR2 SH4_PCIWCR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SH4_PCIMCR 0x1F4 /* Memory Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SH4_PCIPCTR 0x200 /* Port Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SH4_PCIPDTR 0x204 /* Port Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SH4_PCIPDR 0x220 /* Port IO Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* arch/sh/kernel/drivers/pci/ops-sh4.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern struct pci_ops sh4_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int pci_fixup_pcic(struct pci_channel *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct sh4_pci_address_space {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct sh4_pci_address_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct sh4_pci_address_space window0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sh4_pci_address_space window1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline void pci_write_reg(struct pci_channel *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __raw_writel(val, chan->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline unsigned long pci_read_reg(struct pci_channel *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return __raw_readl(chan->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif /* __PCI_SH4_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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