^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic SH7786 PCI-Express operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2010 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pcie-sh7786.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PCI_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PCI_ACCESS_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int sh7786_pcie_config_access(unsigned char access_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct pci_channel *chan = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int dev, func, type, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) dev = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) func = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) type = !!bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (bus->number > 255 || dev > 31 || func > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * While each channel has its own memory-mapped extended config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * space, it's generally only accessible when in endpoint mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * When in root complex mode, the controller is unable to target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * itself with either type 0 or type 1 accesses, and indeed, any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * controller initiated target transfer to its own config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * result in a completer abort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Each channel effectively only supports a single device, but as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * the same channel <-> device access works for any PCI_SLOT()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * value, we cheat a bit here and bind the controller's config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * space to devfn 0 in order to enable self-enumeration. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * case the regular PAR/PDR path is sidelined and the mangled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * config access itself is initiated as a SuperHyway transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (dev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (access_type == PCI_ACCESS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *data = pci_read_reg(chan, PCI_REG(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_write_reg(chan, *data, PCI_REG(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } else if (dev > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Clear errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Set the PIO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (func << 16) | reg, SH4A_PCIEPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Enable the configuration access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Check for master and target aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (access_type == PCI_ACCESS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *data = pci_read_reg(chan, SH4A_PCIEPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pci_write_reg(chan, *data, SH4A_PCIEPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Disable the configuration access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) devfn, where, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret != PCIBIOS_SUCCESSFUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *val = (data >> ((where & 2) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "where=0x%04x size=%d val=0x%08lx\n", bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) devfn, where, size, (unsigned long)*val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int shift, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) devfn, where, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "where=0x%04x size=%d val=%08lx\n", bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) devfn, where, size, (unsigned long)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) shift = (where & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) data &= ~(0xff << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) data |= ((val & 0xff) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else if (size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) shift = (where & 2) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) data &= ~(0xffff << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) data |= ((val & 0xffff) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) devfn, where, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct pci_ops sh7786_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .read = sh7786_pcie_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .write = sh7786_pcie_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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