Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2002 - 2009  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "pci-sh4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Direct access to PCI hardware...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CONFIG_CMD(bus, devfn, where) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Functions for accessing PCI configuration space with type 1 accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			   int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct pci_channel *chan = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	 * PCIPDR may only be accessed as 32 bit words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	 * so we must do byte alignment by hand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	data = pci_read_reg(chan, SH4_PCIPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		*val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		*val = (data >> ((where & 2) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		*val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * Since SH4 only does 32bit access we'll have to do a read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * mask,write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * We'll allow an odd byte offset, though it should be illegal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			 int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct pci_channel *chan = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	data = pci_read_reg(chan, SH4_PCIPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		shift = (where & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		data &= ~(0xff << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		data |= ((val & 0xff) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		shift = (where & 2) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		data &= ~(0xffff << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		data |= ((val & 0xffff) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	pci_write_reg(chan, data, SH4_PCIPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct pci_ops sh4_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.read		= sh4_pci_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.write		= sh4_pci_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* Nothing to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }