^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "pci-sh4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) int pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) switch (slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) case 0: return evt2irq(0x3a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) case 2: return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) case 3: return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) case 4: return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIMCR_MRSET_OFF 0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIMCR_RFSH_OFF 0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Only long word accesses of the PCIC's internal local registers and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * configuration registers from the CPU is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIC_READ(x) readl(PCI_REG(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Description: This function sets up and initializes the pcic, sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * up the BARS, maps the DRAM into the address space etc, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int pci_fixup_pcic(struct pci_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned short bcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Initialize the slave bus controller on the pcic. The values used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * here should not be hardcoded, but they should be taken from the bsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * on the processor, to make this function as generic as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * (i.e. Another sbc may usr different SDRAM timing settings -- in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * for the pcic to work, its settings need to be exactly the same.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mcr = (*(volatile unsigned long*)(SH7751_MCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Enable all interrupts, so we know what to fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Set up standard PCI config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Now turn it on... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PCIC_WRITE(SH7751_PCICR, 0xa5000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Set PCIMBR and PCIIOBR here, assuming a single window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * (16M MEM, 256K IO) is enough. If a larger space is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * needed, the readx/writex and inx/outx functions will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * have to do more (e.g. setting registers for each call).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Set the MBR so PCI address is one-to-one with window,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * meaning all calls go straight through... use BUG_ON to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * catch erroneous assumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Set IOBR for window containing area specified in pci.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* All done, may as well say so... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) printk("SH7751 PCI: Finished initialization of the PCI controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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