Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/sh/drivers/pci/fixups-rts7751r2d.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * RTS7751R2D / LBOXRE2 PCI fixups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2003  Lineo uSolutions, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2004  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright (C) 2007  Nobuhiro Iwamatsu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/lboxre2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <mach/r2d.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pci-sh4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <generated/machtypes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCIMCR_MRSET_OFF	0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCIMCR_RFSH_OFF		0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static u8 rts7751r2d_irq_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	IRQ_PCI_INTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	IRQ_PCI_INTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	IRQ_PCI_INTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	IRQ_PCI_INTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static char lboxre2_irq_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (mach_is_lboxre2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		return lboxre2_irq_tab[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		return rts7751r2d_irq_tab[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int pci_fixup_pcic(struct pci_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	unsigned long bcr1, mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	bcr1 = __raw_readl(SH7751_BCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	pci_write_reg(chan, bcr1, SH4_PCIBCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	/* Enable all interrupts, so we known what to fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	mcr = __raw_readl(SH7751_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	pci_write_reg(chan, mcr, SH4_PCIMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }