Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/sh/drivers/pci/fixups-landisk.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * PCI initialization for the I-O DATA Device, Inc. LANDISK board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2006 kogiidena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2010 Nobuhiro Iwamatsu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pci-sh4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCIMCR_MRSET_OFF	0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCIMCR_RFSH_OFF		0xFFFFFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 * slot0: pin1-4 = irq5,6,7,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	 * slot1: pin1-4 = irq6,7,8,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	 * slot2: pin1-4 = irq7,8,5,6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	 * slot3: pin1-4 = irq8,5,6,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if ((slot | (pin - 1)) > 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		       slot, pin - 1 + 'A');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int pci_fixup_pcic(struct pci_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	unsigned long bcr1, mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	bcr1 = __raw_readl(SH7751_BCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	pci_write_reg(chan, bcr1, SH4_PCIBCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	mcr = __raw_readl(SH7751_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	pci_write_reg(chan, mcr, SH4_PCIMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }