Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/sh/drivers/dma/dma-pvr2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * NEC PowerVR 2 (Dreamcast) DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2003, 2004  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <mach/sysasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static unsigned int xfer_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	if (get_dma_residue(PVR2_CASCADE_CHAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		printk(KERN_WARNING "DMA: SH DMAC did not complete transfer "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		       "on channel %d, waiting..\n", PVR2_CASCADE_CHAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		dma_wait_for_completion(PVR2_CASCADE_CHAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	if (count++ < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		pr_debug("Got a pvr2 dma interrupt for channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			 irq - HW_EVENT_PVR2_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	xfer_complete = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static int pvr2_request_dma(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (__raw_readl(PVR2_DMA_MODE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	__raw_writel(0, PVR2_DMA_LMMODE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int pvr2_get_dma_residue(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return xfer_complete == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int pvr2_xfer_dma(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (chan->sar || !chan->dar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	xfer_complete = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	__raw_writel(chan->dar, PVR2_DMA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	__raw_writel(chan->count, PVR2_DMA_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct dma_ops pvr2_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.request	= pvr2_request_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.get_residue	= pvr2_get_dma_residue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.xfer		= pvr2_xfer_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct dma_info pvr2_dma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.name		= "pvr2_dmac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.nr_channels	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.ops		= &pvr2_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.flags		= DMAC_CHANNELS_TEI_CAPABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int __init pvr2_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (request_irq(HW_EVENT_PVR2_DMA, pvr2_dma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			"pvr2 DMA handler", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		pr_err("Failed to register pvr2 DMA handler interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	request_dma(PVR2_CASCADE_CHAN, "pvr2 cascade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return register_dmac(&pvr2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void __exit pvr2_dma_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	free_dma(PVR2_CASCADE_CHAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	free_irq(HW_EVENT_PVR2_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unregister_dmac(&pvr2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) subsys_initcall(pvr2_dma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) module_exit(pvr2_dma_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_DESCRIPTION("NEC PowerVR 2 DMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_LICENSE("GPL v2");