^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sh/drivers/dma/dma-g2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * G2 bus DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003 - 2006 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <mach/sysasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct g2_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned long g2_addr; /* G2 bus address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned long root_addr; /* Root bus (SH-4) address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned long size; /* Size (in bytes), 32-byte aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long direction; /* Transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long ctrl; /* Transfer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned long chan_enable; /* Channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long xfer_enable; /* Transfer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long xfer_stat; /* Transfer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } __attribute__ ((aligned(32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct g2_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long g2_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long root_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) } __attribute__ ((aligned(16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct g2_dma_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct g2_channel channel[G2_NR_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long pad1[G2_NR_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long wait_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long pad2[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct g2_status status[G2_NR_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } __attribute__ ((aligned(256)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa05f7800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define g2_bytes_remaining(i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ((g2_dma->channel[i].size - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) g2_dma->status[i].size) & 0x0fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static irqreturn_t g2_dma_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (i = 0; i < G2_NR_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (g2_dma->status[i].status & 0x20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int bytes = g2_bytes_remaining(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (likely(bytes == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct dma_info *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct dma_channel *chan = info->channels + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) wake_up(&chan->wait_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int g2_enable_dma(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int chan_nr = chan->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) g2_dma->channel[chan_nr].chan_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) g2_dma->channel[chan_nr].xfer_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int g2_disable_dma(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int chan_nr = chan->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) g2_dma->channel[chan_nr].chan_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) g2_dma->channel[chan_nr].xfer_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int g2_xfer_dma(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int chan_nr = chan->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (chan->sar & 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) printk("g2dma: unaligned source 0x%lx\n", chan->sar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (chan->dar & 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) printk("g2dma: unaligned dest 0x%lx\n", chan->dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Align the count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (chan->count & 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) chan->count = (chan->count + (32 - 1)) & ~(32 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Fixup destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) chan->dar += 0xa0800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Fixup direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) chan->mode = !chan->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) flush_icache_range((unsigned long)chan->sar, chan->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) g2_disable_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) g2_dma->channel[chan_nr].g2_addr = chan->dar & 0x1fffffe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) g2_dma->channel[chan_nr].size = (chan->count & ~31) | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) g2_dma->channel[chan_nr].direction = chan->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * bit 0 - ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * bit 1 - if set, generate a hardware event on transfer completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * bit 2 - ??? something to do with suspend?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) g2_dma->channel[chan_nr].ctrl = 5; /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) g2_enable_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* debug cruft */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "0x%08lx, %ld, %ld, %ld, %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) g2_dma->channel[chan_nr].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) g2_dma->channel[chan_nr].root_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) g2_dma->channel[chan_nr].g2_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) g2_dma->channel[chan_nr].direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) g2_dma->channel[chan_nr].ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) g2_dma->channel[chan_nr].chan_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) g2_dma->channel[chan_nr].xfer_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int g2_get_residue(struct dma_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return g2_bytes_remaining(chan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct dma_ops g2_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .xfer = g2_xfer_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .get_residue = g2_get_residue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct dma_info g2_dma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "g2_dmac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .nr_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .ops = &g2_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .flags = DMAC_CHANNELS_TEI_CAPABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int __init g2_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = request_irq(HW_EVENT_G2_DMA, g2_dma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "g2 DMA handler", &g2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) g2_dma->wait_state = 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) g2_dma->magic = 0x4659404f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = register_dmac(&g2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (unlikely(ret != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) free_irq(HW_EVENT_G2_DMA, &g2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void __exit g2_dma_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) free_irq(HW_EVENT_G2_DMA, &g2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unregister_dmac(&g2_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) subsys_initcall(g2_dma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) module_exit(g2_dma_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_DESCRIPTION("G2 bus DMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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