Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) menu "DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) config SH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	bool "SuperH on-chip DMA controller (DMAC) support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	depends on CPU_SH3 || CPU_SH4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) config SH_DMA_IRQ_MULTI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	depends on SH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	default y if CPU_SUBTYPE_SH7750  || CPU_SUBTYPE_SH7751  || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		     CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		     CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091  || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		     CPU_SUBTYPE_SH7763  || CPU_SUBTYPE_SH7780  || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		     CPU_SUBTYPE_SH7785  || CPU_SUBTYPE_SH7760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) config SH_DMA_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	depends on SH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	bool "SuperH DMA API support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	  SH_DMA_API always enabled DMA API of used SuperH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	  If you want to use DMA ENGINE, you must not enable this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	  Please enable DMA_ENGINE and SH_DMAE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) config NR_ONCHIP_DMA_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	depends on SH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	default "4" if CPU_SUBTYPE_SH7750  || CPU_SUBTYPE_SH7751  || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		       CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		       CPU_SUBTYPE_SH7760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780  || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	default "6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	  This allows you to specify the number of channels that the on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	  DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	  SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) config SH_DMABRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	bool "SH7760 DMABRG support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	depends on CPU_SUBTYPE_SH7760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	  The DMABRG does data transfers from main memory to Audio/USB units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	  of the SH7760.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	  Say Y if you want to use Audio/USB DMA on your SH7760 board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) config PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	tristate "PowerVR 2 DMAC support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	depends on SH_DREAMCAST && SH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	  Selecting this will enable support for the PVR2 DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	  As this chains off of the on-chip DMAC, that must also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	  enabled by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	  This is primarily used by the pvr2fb framebuffer driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	  certain optimizations, but is not necessary for functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	  If in doubt, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) config G2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	tristate "G2 Bus DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	depends on SH_DREAMCAST && SH_DMA_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	  This enables support for the DMA controller for the Dreamcast's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	  G2 bus. Drivers that want this will generally enable this on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	  their own.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	  If in doubt, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) endmenu