Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * sh7724 MMCIF loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2010 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mmc/sh_mmcif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/romimage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MMCIF_BASE      (void __iomem *)0xa4ca0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MSTPCR2		0xa4150038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PTWCR		0xa4050146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PTXCR		0xa4050148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PSELA		0xa405014e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PSELE		0xa4050156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HIZCRC		0xa405015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRVCRA		0xa405018a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	MMCIF_PROGRESS_ENTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	MMCIF_PROGRESS_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	MMCIF_PROGRESS_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	MMCIF_PROGRESS_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SH7724 specific MMCIF loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * loads the romImage from an MMC card starting from block 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * use the following line to write the romImage to an MMC card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	mmcif_update_progress(MMCIF_PROGRESS_ENTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* enable clock to the MMCIF hardware block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* setup pins D7-D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	__raw_writew(0x0000, PTWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	/* setup pins MMC_CLK, MMC_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	__raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	/* select D3-D0 pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	__raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* select D7-D4 pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	__raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	/* disable Hi-Z for the MMC pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	__raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	/* high drive capability for MMC pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	__raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	mmcif_update_progress(MMCIF_PROGRESS_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	/* setup MMCIF hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	sh_mmcif_boot_init(MMCIF_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	mmcif_update_progress(MMCIF_PROGRESS_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	/* load kernel via MMCIF interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	sh_mmcif_boot_do_read(MMCIF_BASE, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	                      (no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			      buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	/* disable clock to the MMCIF hardware block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	mmcif_update_progress(MMCIF_PROGRESS_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }