Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/sh/boards/renesas/sh7763rdp/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Renesas Solutions sh7763rdp board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sh_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <mach/sh7763rdp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/sh7760fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* NOR Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static struct mtd_partition sh7763rdp_nor_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.name = "U-Boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.size = (2 * 128 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.mask_flags = MTD_WRITEABLE,	/* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.name = "Linux-Kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.size = (20 * 128 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.name = "Root Filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static struct physmap_flash_data sh7763rdp_nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.parts = sh7763rdp_nor_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct resource sh7763rdp_nor_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.name = "NOR Flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.end = (64 * 1024 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct platform_device sh7763rdp_nor_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.resource = sh7763rdp_nor_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.platform_data = &sh7763rdp_nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * SH-Ether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * SH Ether of SH7763 has multi IRQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * (0x920,0x940,0x960 -> 0x920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static struct resource sh_eth_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.start  = 0xFEE00800,   /* use eth1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.end    = 0xFEE00F7C - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.flags  = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.start  = 0xFEE01800,   /* TSU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.end    = 0xFEE01FFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.flags  = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.start  = evt2irq(0x920),   /* irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.flags  = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct sh_eth_plat_data sh7763_eth_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.phy = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.phy_interface = PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static struct platform_device sh7763rdp_eth_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.name       = "sh7763-gether",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.resource   = sh_eth_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.num_resources  = ARRAY_SIZE(sh_eth_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.dev        = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.platform_data = &sh7763_eth_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* SH7763 LCDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct resource sh7763rdp_fb_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.start  = 0xFFE80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.end    = 0xFFE80442 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.flags  = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct fb_videomode sh7763fb_videomode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.name = "VGA Monitor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.pixclock = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.left_margin = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.right_margin = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.upper_margin = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.hsync_len = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.vmode = FB_VMODE_NONINTERLACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.flag = FBINFO_FLAG_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct sh7760fb_platdata sh7763fb_def_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.def_mode = &sh7763fb_videomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.ldmtr = (LDMTR_TFT_COLOR_16|LDMTR_MCNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.lddfr = LDDFR_16BPP_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.ldpmmr = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.ldpspr = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.ldaclnr = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.ldickr = 0x1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.rotate = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.novsync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.blank = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct platform_device sh7763rdp_fb_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.name		= "sh7760-lcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.resource	= sh7763rdp_fb_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.num_resources = ARRAY_SIZE(sh7763rdp_fb_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.platform_data = &sh7763fb_def_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct platform_device *sh7763rdp_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	&sh7763rdp_nor_flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	&sh7763rdp_eth_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	&sh7763rdp_fb_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int __init sh7763rdp_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return platform_add_devices(sh7763rdp_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				    ARRAY_SIZE(sh7763rdp_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) device_initcall(sh7763rdp_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void __init sh7763rdp_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Board version check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		printk(KERN_INFO "RTE Standard Configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		printk(KERN_INFO "RTA Standard Configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* USB pin select bits (clear bit 5-2 to 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	__raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* USBH setup port I controls to other (clear bits 4-9 to 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	__raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Select USB Host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	__raw_writew(0x00, USB_USBHSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* For LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* set PTJ7-1, bits 15-2 of PJCR to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* set PTI5, bits 11-10 of PICR to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	__raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	__raw_writew(0, PORT_PKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	__raw_writew(0, PORT_PLCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	__raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* For HAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* bit3-0  0100:HAC & SSI1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	__raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* bit14      1:SSI_HAC_CLK enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	__raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* SH-Ether */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	__raw_writew(0x0, PORT_PFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__raw_writew(0x0, PORT_PFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	__raw_writew(0x0, PORT_PFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/*selects SCIF and MMC other functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	__raw_writew(0x0001, PORT_PSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* MMC clock operates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	__raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	__raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	__raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct sh_machine_vector mv_sh7763rdp __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.mv_name = "sh7763drp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.mv_setup = sh7763rdp_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.mv_init_irq = init_sh7763rdp_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };