Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * linux/arch/sh/boards/renesas/sh7763rdp/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Renesas Solutions SH7763RDP Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2008  Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <mach/sh7763rdp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INTC_BASE		(0xFFD00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define INTC_INT2PRI7   (INTC_BASE+0x4001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define INTC_INT2MSKCR	(INTC_BASE+0x4003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INTC_INT2MSKCR1	(INTC_BASE+0x400D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * Initialize IRQ setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __init init_sh7763rdp_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	/* GPIO enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	__raw_writel(1 << 25, INTC_INT2MSKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	/* enable GPIO interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	__raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		  INTC_INT2PRI7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* USBH enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	__raw_writel(1 << 17, INTC_INT2MSKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/* GETHER enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	__raw_writel(1 << 16, INTC_INT2MSKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	/* DMAC enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	__raw_writel(1 << 8, INTC_INT2MSKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }