Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Renesas Technology Europe SDK7786 Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010  Matt Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2010  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <mach/fpga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/heartbeat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/smp-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static struct resource heartbeat_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.start		= 0x07fff8b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.end		= 0x07fff8b0 + sizeof(u16) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.flags		= IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static struct platform_device heartbeat_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.name		= "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.resource	= &heartbeat_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Dummy supplies, where voltage doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static struct regulator_consumer_supply dummy_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	REGULATOR_SUPPLY("vddvario", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct resource smsc911x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.name		= "smsc911x-memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.start		= 0x07ffff00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.end		= 0x07ffff00 + SZ_256 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.name		= "smsc911x-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.start		= evt2irq(0x2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.end		= evt2irq(0x2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.flags		= IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct smsc911x_platform_config smsc911x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.flags		= SMSC911X_USE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.phy_interface	= PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct platform_device smsc911x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.name		= "smsc911x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.num_resources	= ARRAY_SIZE(smsc911x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.resource	= smsc911x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.platform_data = &smsc911x_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct resource smbus_fpga_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.start		= 0x07fff9e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.end		= 0x07fff9e0 + SZ_32 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct platform_device smbus_fpga_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.name		= "i2c-sdk7786",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.resource	= &smbus_fpga_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static struct resource smbus_pcie_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.start		= 0x07fffc30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.end		= 0x07fffc30 + SZ_32 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static struct platform_device smbus_pcie_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.name		= "i2c-sdk7786",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.id		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.resource	= &smbus_pcie_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		I2C_BOARD_INFO("max6900", 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct platform_device *sh7786_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	&heartbeat_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	&smsc911x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	&smbus_fpga_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	&smbus_pcie_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int sdk7786_i2c_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * Hand over I2C control to the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	tmp = fpga_read_reg(SBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	tmp &= ~SCBR_I2CCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	tmp |= SCBR_I2CMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	fpga_write_reg(tmp, SBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return i2c_register_board_info(0, sdk7786_i2c_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				       ARRAY_SIZE(sdk7786_i2c_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int __init sdk7786_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (unlikely(ret != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return sdk7786_i2c_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) device_initcall(sdk7786_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int sdk7786_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return fpga_read_reg(MODSWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * FPGA-driven PCIe clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * Historically these include the oscillator, clock B (slots 2/3/4) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * everything under a single PCIe clocks enable bit that happens to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * to the same bit position as the oscillator bit for earlier FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * versions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * Given that the legacy clocks have the side-effect of shutting the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * off through the FPGA along with the PCI slots, we simply leave them in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * their initial state and don't bother registering them with the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int sdk7786_pcie_clk_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void sdk7786_pcie_clk_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct sh_clk_ops sdk7786_pcie_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.enable		= sdk7786_pcie_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.disable	= sdk7786_pcie_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct clk sdk7786_pcie_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.ops		= &sdk7786_pcie_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clk_lookup sdk7786_pcie_cl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.con_id		= "pcie_plat_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.clk		= &sdk7786_pcie_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int sdk7786_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * Only handle the EXTAL case, anyone interfacing a crystal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * resonator will need to provide their own input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (test_mode_pin(MODE_PIN9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	clk = clk_get(NULL, "extal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret = clk_set_rate(clk, 33333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * Setup the FPGA clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ret = clk_register(&sdk7786_pcie_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		pr_err("FPGA clock registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	clkdev_add(&sdk7786_pcie_cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void sdk7786_restart(char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	fpga_write_reg(0xa5a5, SRSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void sdk7786_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * It can take up to 20us for the R8C to do its job, back off and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * wait a bit until we've been shut off. Even though newer FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * versions don't set the ACK bit, the latency issue remains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		cpu_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Initialize the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void __init sdk7786_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	pr_info("Renesas Technology Europe SDK7786 support:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	sdk7786_fpga_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	sdk7786_nmi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	machine_ops.restart = sdk7786_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	pm_power_off = sdk7786_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	register_smp_ops(&shx3_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * The Machine Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct sh_machine_vector mv_sdk7786 __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.mv_name		= "SDK7786",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.mv_setup		= sdk7786_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.mv_mode_pins		= sdk7786_mode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.mv_clk_init		= sdk7786_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.mv_init_irq		= sdk7786_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };