Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * SDK7786 FPGA IRQ Controller Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2010  Matt Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2010  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <mach/fpga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	ATA_IRQ_BIT		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	SPI_BUSY_BIT		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	LIRQ5_BIT		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	LIRQ6_BIT		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	LIRQ7_BIT		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	LIRQ8_BIT		= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	KEY_IRQ_BIT		= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	PEN_IRQ_BIT		= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	ETH_IRQ_BIT		= 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	RTC_ALARM_BIT		= 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	CRYSTAL_FAIL_BIT	= 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	ETH_PME_BIT		= 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __init sdk7786_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	/* Enable priority encoding for all IRLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* Clear FPGA interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	fpga_write_reg(0x0000, INTASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	fpga_write_reg(0x0000, INTBSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	/* Unmask FPGA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	tmp = fpga_read_reg(INTAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	tmp &= ~(1 << ETH_IRQ_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	fpga_write_reg(tmp, INTAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }