^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * hp6x0 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/hd64461.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/bl_bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <mach/hp6xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <cpu/dac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/freq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INTR_OFFSET 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STBCR 0xffffff82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STBCR2 0xffffff88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STBCR_STBY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STBCR_MSTP2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCR 0xffffff68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTCNT 0xffffff70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCR_RMODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCR_RFSH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern u8 wakeup_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern u8 wakeup_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void pm_enter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 stbcr, csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u16 frqcr, mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 vbr_new, vbr_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) set_bl_bit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* set wdt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) csr = sh_wdt_read_csr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) csr &= ~WTCSR_TME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) csr |= WTCSR_CKS_4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sh_wdt_write_csr(csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) csr = sh_wdt_read_csr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) sh_wdt_write_cnt(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* disable PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) frqcr = __raw_readw(FRQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __raw_writew(frqcr, FRQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* enable standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) stbcr = __raw_readb(STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* set self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mcr = __raw_readw(MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __raw_writew(mcr & ~MCR_RFSH, MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* set interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) asm volatile("stc vbr, %0" : "=r" (vbr_old));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) vbr_new = get_zeroed_page(GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) memcpy((void*)(vbr_new + INTR_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &wakeup_start, &wakeup_end - &wakeup_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) asm volatile("ldc %0, vbr" : : "r" (vbr_new));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __raw_writew(0, RTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cpu_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) asm volatile("ldc %0, vbr" : : "r" (vbr_old));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) free_page(vbr_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* enable PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) frqcr = __raw_readw(FRQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) frqcr |= FRQCR_PSTBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __raw_writew(frqcr, FRQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) frqcr |= FRQCR_PLLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writew(frqcr, FRQCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writeb(stbcr, STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clear_bl_bit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int hp6x0_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 stbcr, stbcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef CONFIG_HD64461_ENABLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 hd64461_stbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_HD64461_ENABLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) outb(0, HD64461_PCC1CSCIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) scr = inb(HD64461_PCC1SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) scr |= HD64461_PCCSCR_VCC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) outb(scr, HD64461_PCC1SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) hd64461_stbcr = inw(HD64461_STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hd64461_stbcr |= HD64461_STBCR_SPC1ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) outw(hd64461_stbcr, HD64461_STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __raw_writeb(0x1f, DACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) stbcr = __raw_readb(STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __raw_writeb(0x01, STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) stbcr2 = __raw_readb(STBCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __raw_writeb(0x7f , STBCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) outw(0xf07f, HD64461_SCPUCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) outw(0, HD64461_SCPUCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __raw_writeb(stbcr, STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __raw_writeb(stbcr2, STBCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef CONFIG_HD64461_ENABLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) hd64461_stbcr = inw(HD64461_STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) outw(hd64461_stbcr, HD64461_STBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) outb(0x4c, HD64461_PCC1CSCIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) outb(0x00, HD64461_PCC1CSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct platform_suspend_ops hp6x0_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .enter = hp6x0_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .valid = suspend_valid_only_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int __init hp6x0_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) suspend_set_ops(&hp6x0_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) late_initcall(hp6x0_pm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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