Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas Solutions Highlander R7785RP Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2002  Atom Create Engineering Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2006 - 2008  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2007  Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/highlander.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	UNUSED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	/* FPGA specific interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	CF,		/* Compact Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	SMBUS,		/* SMBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	TP,		/* Touch panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	RTC,		/* RTC Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	TH_ALERT,	/* Temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	AX88796,	/* Ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	/* external bus connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	EXT0, EXT1, EXT2, EXT3, EXT4, EXT5, EXT6, EXT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct intc_vect vectors[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	INTC_IRQ(CF, IRQ_CF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	INTC_IRQ(SMBUS, IRQ_SMBUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	INTC_IRQ(TP, IRQ_TP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	INTC_IRQ(RTC, IRQ_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	INTC_IRQ(TH_ALERT, IRQ_TH_ALERT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	INTC_IRQ(EXT0, IRQ_EXT0), INTC_IRQ(EXT1, IRQ_EXT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	INTC_IRQ(EXT2, IRQ_EXT2), INTC_IRQ(EXT3, IRQ_EXT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	INTC_IRQ(EXT6, IRQ_EXT6), INTC_IRQ(EXT7, IRQ_EXT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	INTC_IRQ(AX88796, IRQ_AX88796),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct intc_mask_reg mask_registers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	{ 0xa4000010, 0, 16, /* IRLMCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	  { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	    RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	{ 0xa4000012, 0, 16, /* IRLMCR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	  { 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	    EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static unsigned char irl2irq[HL_NR_IRL] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	IRQ_EXT6, IRQ_EXT7, IRQ_SMBUS, IRQ_TP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	IRQ_RTC, IRQ_TH_ALERT, IRQ_AX88796, IRQ_EXT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	IRQ_EXT1, IRQ_EXT2, IRQ_EXT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			 NULL, mask_registers, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned char * __init highlander_plat_irq_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	printk(KERN_INFO "Using r7785rp interrupt controller.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	__raw_writew(0x0000, PA_IRLSSR1);	/* FPGA IRLSSR1(CF_CD clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	/* Setup the FPGA IRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	__raw_writew(0x0000, PA_IRLPRA);	/* FPGA IRLA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	__raw_writew(0xe598, PA_IRLPRB);	/* FPGA IRLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	__raw_writew(0x7060, PA_IRLPRC);	/* FPGA IRLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	__raw_writew(0x0000, PA_IRLPRD);	/* FPGA IRLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	__raw_writew(0x4321, PA_IRLPRE);	/* FPGA IRLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	__raw_writew(0xdcba, PA_IRLPRF);	/* FPGA IRLF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	register_intc_controller(&intc_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	return irl2irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }