^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sh/boards/dreamcast/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Holly IRQ support for the Sega Dreamcast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is part of the LinuxDC project (www.linuxdc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <mach/sysasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Dreamcast System ASIC Hardware Events -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * hardware events from system peripherals and triggering an SH7750 IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * set in the Event Mask Registers (EMRs). When a hardware event is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * triggered, its corresponding bit in the Event Status Registers (ESRs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * is set, and that bit should be rewritten to the ESR to acknowledge that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * There are three groups of EMRs that parallel the ESRs. Each EMR group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * triggers IRQ 9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * In the kernel, these events are mapped to virtual IRQs so that drivers can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * respond to them as they would a normal interrupt. In order to keep this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * mapping simple, the events are mapped as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 6900/6910 - Events 0-31, IRQ 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 6904/6924 - Events 32-63, IRQ 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 6908/6938 - Events 64-95, IRQ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ESR_BASE 0x005f6900 /* Base event status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EMR_BASE 0x005f6910 /* Base event mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 1 = 0x6920, 2 = 0x6930; also determine the event offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Return the hardware event's bit position within the EMR/ESR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * For each of these *_irq routines, the IRQ passed in is the virtual IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * (logically mapped to the corresponding bit for the hardware event).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Disable the hardware event by masking its bit in its EMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void disable_systemasic_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int irq = data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mask = inl(emr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mask &= ~(1 << EVENT_BIT(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) outl(mask, emr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Enable the hardware event by setting its bit in its EMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void enable_systemasic_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int irq = data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mask = inl(emr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mask |= (1 << EVENT_BIT(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) outl(mask, emr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Acknowledge a hardware event by writing its bit back to its ESR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void mask_ack_systemasic_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int irq = data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) disable_systemasic_irq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) outl((1 << EVENT_BIT(irq)), esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct irq_chip systemasic_int = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "System ASIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .irq_mask = disable_systemasic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .irq_mask_ack = mask_ack_systemasic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .irq_unmask = enable_systemasic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int systemasic_irq_demux(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u32 emr, esr, status, level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __u32 j, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) switch (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) level = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) emr = EMR_BASE + (level << 4) + (level << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) esr = ESR_BASE + (level << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Mask the ESR to filter any spurious, unwanted interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) status = inl(esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) status &= inl(emr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Now scan and find the first set bit as the event to map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (status & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irq = HW_EVENT_IRQ_BASE + j + (level << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Not reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void systemasic_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int irq_base, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR_VALUE(irq_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pr_err("%s: failed hooking irqs\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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