^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas - AP-325RXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (Compatible with Algo System ., LTD. - AP-320A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Yusuke Goda <goda.yuske@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <cpu/sh7723.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mfd/tmio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mtd/sh_flctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/drv-intf/renesas-ceu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <media/i2c/ov772x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <video/sh_mobile_lcdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CEU_BUFFER_MEMORY_SIZE (4 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static phys_addr_t ceu_dma_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Dummy supplies, where voltage doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct regulator_consumer_supply dummy_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) REGULATOR_SUPPLY("vddvario", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) REGULATOR_SUPPLY("vdd33a", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct smsc911x_platform_config smsc911x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .phy_interface = PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .flags = SMSC911X_USE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct resource smsc9118_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .start = 0xb6080000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .end = 0xb60fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .start = evt2irq(0x660),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .end = evt2irq(0x660),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct platform_device smsc9118_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "smsc911x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .num_resources = ARRAY_SIZE(smsc9118_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .resource = smsc9118_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .platform_data = &smsc911x_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * If this area erased, this board can not boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .size = (1 * 1024 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .mask_flags = MTD_WRITEABLE, /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .size = (2 * 1024 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "free-area0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .size = ((7 * 1024 * 1024) + (512 * 1024)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "CPLD-Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .mask_flags = MTD_WRITEABLE, /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .size = (1024 * 128 * 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "free-area1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct physmap_flash_data ap325rxa_nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .parts = ap325rxa_nor_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct resource ap325rxa_nor_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "NOR Flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .start = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .end = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct platform_device ap325rxa_nor_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .resource = ap325rxa_nor_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .platform_data = &ap325rxa_nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct mtd_partition nand_partition_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "nand_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct resource nand_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .start = 0xa4530000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .end = 0xa45300ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct sh_flctl_platform_data nand_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .parts = nand_partition_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .nr_parts = ARRAY_SIZE(nand_partition_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .has_hwecc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct platform_device nand_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "sh_flctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .resource = nand_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .num_resources = ARRAY_SIZE(nand_flash_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .platform_data = &nand_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FPGA_LCDREG 0xB4100180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FPGA_BKLREG 0xB4100212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FPGA_LCDREG_VAL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PORT_MSELCRB 0xA4050182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PORT_HIZCRC 0xA405015C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PORT_DRVCRA 0xA405018A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PORT_DRVCRB 0xA405018C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int ap320_wvga_set_brightness(int brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (brightness) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) gpio_set_value(GPIO_PTS3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __raw_writew(0x100, FPGA_BKLREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __raw_writew(0, FPGA_BKLREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpio_set_value(GPIO_PTS3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ap320_wvga_power_on(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* ASD AP-320/325 LCD ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void ap320_wvga_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* ASD AP-320/325 LCD OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __raw_writew(0, FPGA_LCDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct fb_videomode ap325rxa_lcdc_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "LB070WV1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .left_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .right_margin = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .hsync_len = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .upper_margin = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .lower_margin = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .sync = 0, /* hsync and vsync are active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct sh_mobile_lcdc_info lcdc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .clock_source = LCDC_CLK_EXTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .ch[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .chan = LCDC_CHAN_MAINLCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .fourcc = V4L2_PIX_FMT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .interface_type = RGB18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .clock_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .lcd_modes = ap325rxa_lcdc_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .panel_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .width = 152, /* 7.0 inch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .height = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .display_on = ap320_wvga_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .display_off = ap320_wvga_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .bl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "sh_mobile_lcdc_bl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .max_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .set_brightness = ap320_wvga_set_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct resource lcdc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "LCDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .start = 0xfe940000, /* P4-only space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .end = 0xfe942fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .start = evt2irq(0x580),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct platform_device lcdc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "sh_mobile_lcdc_fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .num_resources = ARRAY_SIZE(lcdc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .resource = lcdc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .platform_data = &lcdc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Powerdown/reset gpios for CEU image sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct gpiod_lookup_table ov7725_gpios = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .dev_id = "0-0021",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GPIO_LOOKUP("sh7723_pfc", GPIO_PTZ5, "reset", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct ceu_platform_data ceu0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .num_subdevs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .subdevs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { /* [0] = ov7725 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .bus_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .bus_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .i2c_adapter_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .i2c_address = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct resource ceu_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "CEU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .start = 0xfe910000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .end = 0xfe91009f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .start = evt2irq(0x880),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct platform_device ap325rxa_ceu_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "renesas-ceu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .id = 0, /* "ceu.0" clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .num_resources = ARRAY_SIZE(ceu_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .resource = ceu_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .platform_data = &ceu0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct regulator_consumer_supply fixed3v3_power_consumers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct resource sdhi0_cn3_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "SDHI0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .start = 0x04ce0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .end = 0x04ce00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .start = evt2irq(0xe80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct tmio_mmc_data sdhi0_cn3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .capabilities = MMC_CAP_SDIO_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct platform_device sdhi0_cn3_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "sh_mobile_sdhi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .id = 0, /* "sdhi0" clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .resource = sdhi0_cn3_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .platform_data = &sdhi0_cn3_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct resource sdhi1_cn7_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "SDHI1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .start = 0x04cf0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .end = 0x04cf00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .start = evt2irq(0x4e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct tmio_mmc_data sdhi1_cn7_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .capabilities = MMC_CAP_SDIO_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct platform_device sdhi1_cn7_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "sh_mobile_sdhi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .id = 1, /* "sdhi1" clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .resource = sdhi1_cn7_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .platform_data = &sdhi1_cn7_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct ov772x_camera_info ov7725_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct i2c_board_info ap325rxa_i2c_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) I2C_BOARD_INFO("pcf8563", 0x51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) I2C_BOARD_INFO("ov772x", 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .platform_data = &ov7725_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct platform_device *ap325rxa_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) &smsc9118_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) &ap325rxa_nor_flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) &lcdc_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) &nand_flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) &sdhi0_cn3_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) &sdhi1_cn7_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) extern char ap325rxa_sdram_enter_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) extern char ap325rxa_sdram_enter_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) extern char ap325rxa_sdram_leave_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) extern char ap325rxa_sdram_leave_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int __init ap325rxa_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* register board specific self-refresh code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &ap325rxa_sdram_enter_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &ap325rxa_sdram_enter_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &ap325rxa_sdram_leave_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &ap325rxa_sdram_leave_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* LD3 and LD4 LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) gpio_request(GPIO_PTX5, NULL); /* RUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpio_direction_output(GPIO_PTX5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gpio_export(GPIO_PTX5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) gpio_direction_output(GPIO_PTX4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) gpio_export(GPIO_PTX4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* SW1 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) gpio_request(GPIO_PTF7, NULL); /* MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) gpio_direction_input(GPIO_PTF7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gpio_export(GPIO_PTF7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* LCDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) gpio_request(GPIO_FN_LCDD15, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) gpio_request(GPIO_FN_LCDD14, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) gpio_request(GPIO_FN_LCDD13, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gpio_request(GPIO_FN_LCDD12, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) gpio_request(GPIO_FN_LCDD11, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) gpio_request(GPIO_FN_LCDD10, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) gpio_request(GPIO_FN_LCDD9, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) gpio_request(GPIO_FN_LCDD8, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gpio_request(GPIO_FN_LCDD7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) gpio_request(GPIO_FN_LCDD6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) gpio_request(GPIO_FN_LCDD5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) gpio_request(GPIO_FN_LCDD4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) gpio_request(GPIO_FN_LCDD3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) gpio_request(GPIO_FN_LCDD2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gpio_request(GPIO_FN_LCDD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) gpio_request(GPIO_FN_LCDD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) gpio_request(GPIO_FN_LCDDCK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) gpio_request(GPIO_FN_LCDVEPWC, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) gpio_request(GPIO_FN_LCDVCPWC, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) gpio_request(GPIO_FN_LCDVSYN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) gpio_request(GPIO_FN_LCDHSYN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) gpio_request(GPIO_FN_LCDDISP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) gpio_request(GPIO_FN_LCDDON, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* LCD backlight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gpio_request(GPIO_PTS3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gpio_direction_output(GPIO_PTS3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* CEU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) gpio_request(GPIO_FN_VIO_CLK2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) gpio_request(GPIO_FN_VIO_VD2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) gpio_request(GPIO_FN_VIO_HD2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) gpio_request(GPIO_FN_VIO_FLD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) gpio_request(GPIO_FN_VIO_CKO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) gpio_request(GPIO_FN_VIO_D15, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) gpio_request(GPIO_FN_VIO_D14, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) gpio_request(GPIO_FN_VIO_D13, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpio_request(GPIO_FN_VIO_D12, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) gpio_request(GPIO_FN_VIO_D11, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) gpio_request(GPIO_FN_VIO_D10, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gpio_request(GPIO_FN_VIO_D9, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) gpio_request(GPIO_FN_VIO_D8, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpio_request(GPIO_PTZ7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gpio_request(GPIO_PTZ6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) gpio_request(GPIO_PTZ5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) gpio_request(GPIO_PTZ4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) gpio_request(GPIO_FN_FCE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) gpio_request(GPIO_FN_NAF7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) gpio_request(GPIO_FN_NAF6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) gpio_request(GPIO_FN_NAF5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) gpio_request(GPIO_FN_NAF4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gpio_request(GPIO_FN_NAF3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) gpio_request(GPIO_FN_NAF2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) gpio_request(GPIO_FN_NAF1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) gpio_request(GPIO_FN_NAF0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) gpio_request(GPIO_FN_FCDE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) gpio_request(GPIO_FN_FOE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) gpio_request(GPIO_FN_FSC, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) gpio_request(GPIO_FN_FWE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) gpio_request(GPIO_FN_FRB, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __raw_writew(0, PORT_HIZCRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) __raw_writew(0xFFFF, PORT_DRVCRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __raw_writew(0xFFFF, PORT_DRVCRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* SDHI0 - CN3 - SD CARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* SDHI1 - CN7 - MICRO SD CARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) gpio_request(GPIO_FN_SDHI1CD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) gpio_request(GPIO_FN_SDHI1D3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) gpio_request(GPIO_FN_SDHI1D2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) gpio_request(GPIO_FN_SDHI1D1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) gpio_request(GPIO_FN_SDHI1D0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) gpio_request(GPIO_FN_SDHI1CMD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) gpio_request(GPIO_FN_SDHI1CLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Add a clock alias for ov7725 xclk source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clk_add_alias(NULL, "0-0021", "video_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Register RSTB gpio for ov7725 camera sensor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) gpiod_add_lookup_table(&ov7725_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) i2c_register_board_info(0, ap325rxa_i2c_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ARRAY_SIZE(ap325rxa_i2c_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Initialize CEU platform device separately to map memory first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) device_initialize(&ap325rxa_ceu_device.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dma_declare_coherent_memory(&ap325rxa_ceu_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ceu_dma_membase, ceu_dma_membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) platform_device_add(&ap325rxa_ceu_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return platform_add_devices(ap325rxa_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ARRAY_SIZE(ap325rxa_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) arch_initcall(ap325rxa_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Return the board specific boot mode pin configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int ap325rxa_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* MD0=0, MD1=0, MD2=0: Clock Mode 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * MD3=0: 16-bit Area0 Bus Width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * MD5=1: Little Endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * TSTMD=1, MD8=1: Test Mode Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return MODE_PIN5 | MODE_PIN8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Reserve a portion of memory for CEU buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void __init ap325rxa_mv_mem_reserve(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) phys = memblock_phys_alloc(size, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) panic("Failed to allocate CEU memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) memblock_free(phys, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) memblock_remove(phys, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ceu_dma_membase = phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static struct sh_machine_vector mv_ap325rxa __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .mv_name = "AP-325RXA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .mv_mode_pins = ap325rxa_mode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mv_mem_reserve = ap325rxa_mv_mem_reserve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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