^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas Technology Corp. SH7786 Urquell Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009, 2010 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on board-sh7785lcr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2008 Yoshihiro Shimoda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/urquell.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <cpu/sh7786.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/heartbeat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/smp-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * bit 1234 5678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * SW1 0101 0010 -> Pck 33MHz version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * (1101 0010) Pck 66MHz version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * SW2 0x1x xxxx -> little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 29bit mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * SW47 0001 1000 -> CS0 : on-board flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * CS1 : SRAM, registers, LAN, PCMCIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 38400 bps for SCIF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 0x00000000 - 0x04000000 (CS0) Nor Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0x04000000 - 0x04200000 (CS1) SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 0x05000000 - 0x05800000 (CS1) on board register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 0x05800000 - 0x06000000 (CS1) LAN91C111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 0x06000000 - 0x06400000 (CS1) PCMCIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 0x10000000 - 0x14000000 (CS4) PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 0x1C000000 - (CS7) SH7786 Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* HeartBeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct resource heartbeat_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .start = BOARDREG(SLEDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .end = BOARDREG(SLEDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct platform_device heartbeat_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .resource = &heartbeat_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* LAN91C111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct smc91x_platdata smc91x_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct resource smc91x_eth_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "SMC91C111" ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .start = 0x05800300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .end = 0x0580030f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .start = evt2irq(0x360),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct platform_device smc91x_eth_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .num_resources = ARRAY_SIZE(smc91x_eth_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .resource = smc91x_eth_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .platform_data = &smc91x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Nor Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct mtd_partition nor_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "loader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .offset = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .size = SZ_512K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .mask_flags = MTD_WRITEABLE, /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "bootenv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .size = SZ_512K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .mask_flags = MTD_WRITEABLE, /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct physmap_flash_data nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .parts = nor_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .nr_parts = ARRAY_SIZE(nor_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct resource nor_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .start = NOR_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct platform_device nor_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .platform_data = &nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .num_resources = ARRAY_SIZE(nor_flash_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .resource = nor_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct platform_device *urquell_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &heartbeat_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &smc91x_eth_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &nor_flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int __init urquell_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) gpio_request(GPIO_FN_USB_OVC0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gpio_request(GPIO_FN_USB_PENC0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* enable LAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UBOARDREG(IRL2MSKR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return platform_add_devices(urquell_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ARRAY_SIZE(urquell_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) device_initcall(urquell_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void urquell_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __raw_writew(0xa5a5, UBOARDREG(SRSTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __init urquell_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int urquell_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return __raw_readw(UBOARDREG(MDSWMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int urquell_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Only handle the EXTAL case, anyone interfacing a crystal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * resonator will need to provide their own input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (test_mode_pin(MODE_PIN9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk = clk_get(NULL, "extal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = clk_set_rate(clk, 33333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Initialize the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void __init urquell_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pm_power_off = urquell_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) register_smp_ops(&shx3_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * The Machine Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct sh_machine_vector mv_urquell __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .mv_name = "Urquell",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .mv_setup = urquell_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .mv_init_irq = urquell_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .mv_mode_pins = urquell_mode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .mv_clk_init = urquell_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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