^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas Technology Corp. R0P7785LC0011RL Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Yoshihiro Shimoda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sm501.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sm501-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/i2c-pca-platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c-algo-pca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb/r8a66597.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <mach/sh7785lcr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <cpu/sh7785.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/heartbeat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/bl_bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * NOTE: This board has 2 physical memory maps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct resource heartbeat_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .start = PLD_LEDCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .end = PLD_LEDCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct platform_device heartbeat_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .name = "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .resource = &heartbeat_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct mtd_partition nor_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .name = "loader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .offset = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .size = 512 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = "bootenv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .size = 512 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .size = 4 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct physmap_flash_data nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .parts = nor_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .nr_parts = ARRAY_SIZE(nor_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct resource nor_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .start = NOR_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct platform_device nor_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .platform_data = &nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .num_resources = ARRAY_SIZE(nor_flash_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .resource = nor_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct r8a66597_platdata r8a66597_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .vif = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct resource r8a66597_usb_host_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .start = R8A66597_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .end = R8A66597_ADDR + R8A66597_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .start = evt2irq(0x240),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .end = evt2irq(0x240),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct platform_device r8a66597_usb_host_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "r8a66597_hcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .dma_mask = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .coherent_dma_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .platform_data = &r8a66597_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .resource = r8a66597_usb_host_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct resource sm501_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .start = SM107_MEM_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .start = SM107_REG_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .start = evt2irq(0x340),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct fb_videomode sm501_default_mode_crt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .pixclock = 35714, /* 28MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .left_margin = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .upper_margin = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .lower_margin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .hsync_len = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct fb_videomode sm501_default_mode_pnl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .pixclock = 40000, /* 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .left_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .upper_margin = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .lower_margin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .hsync_len = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .def_bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .def_mode = &sm501_default_mode_pnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = SM501FB_FLAG_USE_INIT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SM501FB_FLAG_USE_HWCURSOR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SM501FB_FLAG_USE_HWACCEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SM501FB_FLAG_DISABLE_AT_EXIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SM501FB_FLAG_PANEL_NO_VBIASEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .def_bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .def_mode = &sm501_default_mode_crt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = SM501FB_FLAG_USE_INIT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SM501FB_FLAG_USE_HWCURSOR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SM501FB_FLAG_USE_HWACCEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SM501FB_FLAG_DISABLE_AT_EXIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct sm501_platdata_fb sm501_fb_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .fb_route = SM501_FB_OWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .fb_crt = &sm501_pdata_fbsub_crt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .fb_pnl = &sm501_pdata_fbsub_pnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct sm501_initdata sm501_initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .gpio_high = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .set = 0x00001fe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .mask = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .devices = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .mclk = 84 * 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .m1xclk = 112 * 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct sm501_platdata sm501_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .init = &sm501_initdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .fb = &sm501_fb_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_device sm501_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "sm501",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .platform_data = &sm501_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_resources = ARRAY_SIZE(sm501_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .resource = sm501_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct resource i2c_proto_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .start = PCA9564_PROTO_32BIT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .start = evt2irq(0x380),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .end = evt2irq(0x380),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct resource i2c_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .start = PCA9564_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .end = PCA9564_ADDR + PCA9564_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .start = evt2irq(0x380),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .end = evt2irq(0x380),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct gpiod_lookup_table i2c_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .dev_id = "i2c.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GPIO_LOOKUP("pfc-sh7757", 0, "reset-gpios", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .i2c_clock_speed = I2C_PCA_CON_330kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .timeout = HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_device i2c_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "i2c-pca-platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .platform_data = &i2c_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_resources = ARRAY_SIZE(i2c_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .resource = i2c_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_device *sh7785lcr_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &heartbeat_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) &nor_flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &r8a66597_usb_host_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) &sm501_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &i2c_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) I2C_BOARD_INFO("r2025sd", 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int __init sh7785lcr_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) i2c_register_board_info(0, sh7785lcr_i2c_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ARRAY_SIZE(sh7785lcr_i2c_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (mach_is_sh7785lcr_pt()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) i2c_device.resource = i2c_proto_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) gpiod_add_lookup_table(&i2c_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return platform_add_devices(sh7785lcr_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ARRAY_SIZE(sh7785lcr_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) device_initcall(sh7785lcr_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Initialize IRQ setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void __init init_sh7785lcr_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) plat_irq_setup_pins(IRQ_MODE_IRQ7654);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) plat_irq_setup_pins(IRQ_MODE_IRQ3210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int sh7785lcr_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk = clk_get(NULL, "extal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = clk_set_rate(clk, 33333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void sh7785lcr_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) p = ioremap(PLD_POFCR, PLD_POFCR + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) printk(KERN_ERR "%s: ioremap error.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *p = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) iounmap(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) set_bl_bit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Initialize the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void __init sh7785lcr_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void __iomem *sm501_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pm_power_off = sh7785lcr_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* sm501 DRAM configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sm501_reg = ioremap(SM107_REG_ADDR, SM501_DRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!sm501_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) printk(KERN_ERR "%s: ioremap error.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) iounmap(sm501_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Return the board specific boot mode pin configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int sh7785lcr_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* These are the factory default settings of S1 and S2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * If you change these dip switches then you will need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * adjust the values below as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) value |= MODE_PIN4; /* Clock Mode 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) value |= MODE_PIN5; /* 32-bit Area0 bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) value |= MODE_PIN6; /* 32-bit Area0 bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) value |= MODE_PIN8; /* Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) value |= MODE_PIN9; /* Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) value |= MODE_PIN14; /* No PLL step-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * The Machine Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct sh_machine_vector mv_sh7785lcr __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mv_name = "SH7785LCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .mv_setup = sh7785lcr_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .mv_clk_init = sh7785lcr_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .mv_init_irq = init_sh7785lcr_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .mv_mode_pins = sh7785lcr_mode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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