^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas R0P7757LC0012RL Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/tmio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mmc/sh_mmcif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sh_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/renesas_usbhs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <cpu/sh7757.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/heartbeat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct resource heartbeat_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .start = 0xffec005c, /* PUDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .end = 0xffec005c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct heartbeat_data heartbeat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .bit_pos = heartbeat_bit_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .flags = HEARTBEAT_INVERTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct platform_device heartbeat_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .platform_data = &heartbeat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .resource = &heartbeat_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Fast Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GBECONT 0xffc10100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GBECONT_RMII1 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GBECONT_RMII0 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void sh7757_eth_set_mdio_gate(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (((unsigned long)addr & 0x00000fff) < 0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct resource sh_eth0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .start = 0xfef00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .end = 0xfef001ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .start = evt2irq(0xc80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .end = evt2irq(0xc80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct sh_eth_plat_data sh7757_eth0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .phy = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .set_mdio_gate = sh7757_eth_set_mdio_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct platform_device sh7757_eth0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "sh7757-ether",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .resource = sh_eth0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .num_resources = ARRAY_SIZE(sh_eth0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .platform_data = &sh7757_eth0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct resource sh_eth1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .start = 0xfef00800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .end = 0xfef009ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .start = evt2irq(0xc80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .end = evt2irq(0xc80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct sh_eth_plat_data sh7757_eth1_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .phy = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .set_mdio_gate = sh7757_eth_set_mdio_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct platform_device sh7757_eth1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "sh7757-ether",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .resource = sh_eth1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .num_resources = ARRAY_SIZE(sh_eth1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .platform_data = &sh7757_eth1_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void sh7757_eth_giga_set_mdio_gate(void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (((unsigned long)addr & 0x00000fff) < 0x0800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gpio_set_value(GPIO_PTT4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gpio_set_value(GPIO_PTT4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct resource sh_eth_giga0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .start = 0xfee00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .end = 0xfee007ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* TSU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .start = 0xfee01800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .end = 0xfee01fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .start = evt2irq(0x2960),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .end = evt2irq(0x2960),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .phy = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct platform_device sh7757_eth_giga0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "sh7757-gether",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .resource = sh_eth_giga0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .platform_data = &sh7757_eth_giga0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct resource sh_eth_giga1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .start = 0xfee00800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .end = 0xfee00fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* TSU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .start = 0xfee01800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .end = 0xfee01fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .start = evt2irq(0x2980),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .end = evt2irq(0x2980),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .phy = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct platform_device sh7757_eth_giga1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "sh7757-gether",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .resource = sh_eth_giga1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .id = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .platform_data = &sh7757_eth_giga1_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct regulator_consumer_supply fixed3v3_power_consumers[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SH_MMCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct resource sh_mmcif_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .start = 0xffcb0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .end = 0xffcb00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .start = evt2irq(0x1c60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .start = evt2irq(0x1c80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct sh_mmcif_plat_data sh_mmcif_plat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .sup_pclk = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MMC_CAP_NONREMOVABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct platform_device sh_mmcif_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "sh_mmcif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .platform_data = &sh_mmcif_plat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .num_resources = ARRAY_SIZE(sh_mmcif_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .resource = sh_mmcif_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* SDHI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct tmio_mmc_data sdhi_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .capabilities = MMC_CAP_SD_HIGHSPEED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct resource sdhi_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .start = 0xffe50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .end = 0xffe500ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .start = evt2irq(0x480),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_device sdhi_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "sh_mobile_sdhi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_resources = ARRAY_SIZE(sdhi_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .resource = sdhi_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .platform_data = &sdhi_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int usbhs0_get_id(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return USBHS_GADGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct renesas_usbhs_platform_info usb0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .platform_callback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .get_id = usbhs0_get_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .driver_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .buswait_bwait = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct resource usb0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .start = 0xfe450000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .end = 0xfe4501ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .start = evt2irq(0x840),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .end = evt2irq(0x840),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct platform_device usb0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .name = "renesas_usbhs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .platform_data = &usb0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .num_resources = ARRAY_SIZE(usb0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .resource = usb0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct platform_device *sh7757lcr_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &heartbeat_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) &sh7757_eth0_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) &sh7757_eth1_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) &sh7757_eth_giga0_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &sh7757_eth_giga1_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) &sh_mmcif_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) &sdhi_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &usb0_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct flash_platform_data spi_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .name = "m25p80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .type = "m25px64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct spi_board_info spi_board_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .modalias = "m25p80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .max_speed_hz = 25000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .platform_data = &spi_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int __init sh7757lcr_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* RGMII (PTA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) gpio_request(GPIO_FN_ET0_MDC, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) gpio_request(GPIO_FN_ET0_MDIO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) gpio_request(GPIO_FN_ET1_MDC, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) gpio_request(GPIO_FN_ET1_MDIO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* ONFI (PTB, PTZ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) gpio_request(GPIO_FN_ON_NRE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) gpio_request(GPIO_FN_ON_NWE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) gpio_request(GPIO_FN_ON_NWP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) gpio_request(GPIO_FN_ON_NCE0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) gpio_request(GPIO_FN_ON_R_B0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) gpio_request(GPIO_FN_ON_ALE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) gpio_request(GPIO_FN_ON_CLE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) gpio_request(GPIO_FN_ON_DQ7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) gpio_request(GPIO_FN_ON_DQ6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gpio_request(GPIO_FN_ON_DQ5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) gpio_request(GPIO_FN_ON_DQ4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) gpio_request(GPIO_FN_ON_DQ3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) gpio_request(GPIO_FN_ON_DQ2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) gpio_request(GPIO_FN_ON_DQ1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) gpio_request(GPIO_FN_ON_DQ0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* IRQ8 to 0 (PTB, PTC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) gpio_request(GPIO_FN_IRQ8, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) gpio_request(GPIO_FN_IRQ7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) gpio_request(GPIO_FN_IRQ6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) gpio_request(GPIO_FN_IRQ5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) gpio_request(GPIO_FN_IRQ4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) gpio_request(GPIO_FN_IRQ3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) gpio_request(GPIO_FN_IRQ2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) gpio_request(GPIO_FN_IRQ1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) gpio_request(GPIO_FN_IRQ0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* SPI0 (PTD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) gpio_request(GPIO_FN_SP0_MOSI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) gpio_request(GPIO_FN_SP0_MISO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) gpio_request(GPIO_FN_SP0_SCK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) gpio_request(GPIO_FN_SP0_SS0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) gpio_request(GPIO_FN_SP0_SS1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) gpio_request(GPIO_FN_SP0_SS2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) gpio_request(GPIO_FN_SP0_SS3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* RMII 0/1 (PTE, PTF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) gpio_request(GPIO_FN_RMII0_TXD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) gpio_request(GPIO_FN_RMII0_TXD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) gpio_request(GPIO_FN_RMII0_TXEN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) gpio_request(GPIO_FN_RMII0_RXD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) gpio_request(GPIO_FN_RMII0_RXD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) gpio_request(GPIO_FN_RMII1_TXD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) gpio_request(GPIO_FN_RMII1_TXD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) gpio_request(GPIO_FN_RMII1_TXEN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) gpio_request(GPIO_FN_RMII1_RXD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) gpio_request(GPIO_FN_RMII1_RXD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* eMMC (PTG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) gpio_request(GPIO_FN_MMCCLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) gpio_request(GPIO_FN_MMCCMD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) gpio_request(GPIO_FN_MMCDAT7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) gpio_request(GPIO_FN_MMCDAT6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) gpio_request(GPIO_FN_MMCDAT5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gpio_request(GPIO_FN_MMCDAT4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) gpio_request(GPIO_FN_MMCDAT3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gpio_request(GPIO_FN_MMCDAT2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) gpio_request(GPIO_FN_MMCDAT1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gpio_request(GPIO_FN_MMCDAT0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* LPC (PTG, PTH, PTQ, PTU) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) gpio_request(GPIO_FN_SERIRQ, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) gpio_request(GPIO_FN_LPCPD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpio_request(GPIO_FN_LDRQ, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gpio_request(GPIO_FN_WP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) gpio_request(GPIO_FN_FMS0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gpio_request(GPIO_FN_LAD3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) gpio_request(GPIO_FN_LAD2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) gpio_request(GPIO_FN_LAD1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gpio_request(GPIO_FN_LAD0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gpio_request(GPIO_FN_LFRAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) gpio_request(GPIO_FN_LRESET, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) gpio_request(GPIO_FN_LCLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gpio_request(GPIO_FN_LGPIO7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) gpio_request(GPIO_FN_LGPIO6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) gpio_request(GPIO_FN_LGPIO5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) gpio_request(GPIO_FN_LGPIO4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* SPI1 (PTH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gpio_request(GPIO_FN_SP1_MOSI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) gpio_request(GPIO_FN_SP1_MISO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) gpio_request(GPIO_FN_SP1_SCK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) gpio_request(GPIO_FN_SP1_SS0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gpio_request(GPIO_FN_SP1_SS1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* SDHI (PTI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) gpio_request(GPIO_FN_SD_WP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) gpio_request(GPIO_FN_SD_CD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) gpio_request(GPIO_FN_SD_CLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gpio_request(GPIO_FN_SD_CMD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) gpio_request(GPIO_FN_SD_D3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gpio_request(GPIO_FN_SD_D2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) gpio_request(GPIO_FN_SD_D1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) gpio_request(GPIO_FN_SD_D0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* SCIF3/4 (PTJ, PTW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) gpio_request(GPIO_FN_RTS3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) gpio_request(GPIO_FN_CTS3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) gpio_request(GPIO_FN_TXD3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) gpio_request(GPIO_FN_RXD3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) gpio_request(GPIO_FN_RTS4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gpio_request(GPIO_FN_RXD4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gpio_request(GPIO_FN_TXD4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) gpio_request(GPIO_FN_CTS4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* SERMUX (PTK, PTL, PTO, PTV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) gpio_request(GPIO_FN_COM2_TXD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) gpio_request(GPIO_FN_COM2_RXD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) gpio_request(GPIO_FN_COM2_RTS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) gpio_request(GPIO_FN_COM2_CTS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) gpio_request(GPIO_FN_COM2_DTR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) gpio_request(GPIO_FN_COM2_DSR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) gpio_request(GPIO_FN_COM2_DCD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpio_request(GPIO_FN_COM2_RI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) gpio_request(GPIO_FN_RAC_RXD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) gpio_request(GPIO_FN_RAC_RTS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gpio_request(GPIO_FN_RAC_CTS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) gpio_request(GPIO_FN_RAC_DTR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) gpio_request(GPIO_FN_RAC_DSR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpio_request(GPIO_FN_RAC_DCD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) gpio_request(GPIO_FN_RAC_TXD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) gpio_request(GPIO_FN_COM1_TXD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) gpio_request(GPIO_FN_COM1_RXD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) gpio_request(GPIO_FN_COM1_RTS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) gpio_request(GPIO_FN_COM1_CTS, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* IIC (PTM, PTR, PTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) gpio_request(GPIO_FN_SDA7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) gpio_request(GPIO_FN_SCL7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) gpio_request(GPIO_FN_SDA6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) gpio_request(GPIO_FN_SCL6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) gpio_request(GPIO_FN_SDA5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) gpio_request(GPIO_FN_SCL5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) gpio_request(GPIO_FN_SDA4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gpio_request(GPIO_FN_SCL4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) gpio_request(GPIO_FN_SDA3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) gpio_request(GPIO_FN_SCL3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) gpio_request(GPIO_FN_SDA2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) gpio_request(GPIO_FN_SCL2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) gpio_request(GPIO_FN_SDA1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) gpio_request(GPIO_FN_SCL1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) gpio_request(GPIO_FN_SDA0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) gpio_request(GPIO_FN_SCL0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* USB (PTN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) gpio_request(GPIO_FN_VBUS_EN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) gpio_request(GPIO_FN_VBUS_OC, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* SGPIO1/0 (PTN, PTO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) gpio_request(GPIO_FN_SGPIO1_DI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) gpio_request(GPIO_FN_SGPIO1_DO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) gpio_request(GPIO_FN_SGPIO0_DI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) gpio_request(GPIO_FN_SGPIO0_DO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* WDT (PTN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) gpio_request(GPIO_FN_SUB_CLKIN, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* System (PTT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) gpio_request(GPIO_FN_STATUS1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) gpio_request(GPIO_FN_STATUS0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* PWMX (PTT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) gpio_request(GPIO_FN_PWMX1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) gpio_request(GPIO_FN_PWMX0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* R-SPI (PTV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) gpio_request(GPIO_FN_R_SPI_MISO, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* EVC (PTV, PTW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) gpio_request(GPIO_FN_EVENT7, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) gpio_request(GPIO_FN_EVENT6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) gpio_request(GPIO_FN_EVENT5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) gpio_request(GPIO_FN_EVENT4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) gpio_request(GPIO_FN_EVENT3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) gpio_request(GPIO_FN_EVENT2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) gpio_request(GPIO_FN_EVENT1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gpio_request(GPIO_FN_EVENT0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* LED for heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) gpio_request(GPIO_PTU3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) gpio_direction_output(GPIO_PTU3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) gpio_request(GPIO_PTU2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) gpio_direction_output(GPIO_PTU2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) gpio_request(GPIO_PTU1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gpio_direction_output(GPIO_PTU1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gpio_request(GPIO_PTU0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) gpio_direction_output(GPIO_PTU0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* control for MDIO of Gigabit Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) gpio_request(GPIO_PTT4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) gpio_direction_output(GPIO_PTT4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* control for eMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) gpio_direction_output(GPIO_PTT7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) gpio_direction_output(GPIO_PTT6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) gpio_direction_output(GPIO_PTT5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* register SPI device information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) spi_register_board_info(spi_board_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ARRAY_SIZE(spi_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* General platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return platform_add_devices(sh7757lcr_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ARRAY_SIZE(sh7757lcr_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) arch_initcall(sh7757lcr_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Initialize IRQ setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void __init init_sh7757lcr_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) plat_irq_setup_pins(IRQ_MODE_IRQ7654);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) plat_irq_setup_pins(IRQ_MODE_IRQ3210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Initialize the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void __init sh7757lcr_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int sh7757lcr_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* These are the factory default settings of S3 (Low active).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * If you change these dip switches then you will need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * adjust the values below as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) value |= MODE_PIN0; /* Clock Mode: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* The Machine Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct sh_machine_vector mv_sh7757lcr __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .mv_name = "SH7757LCR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .mv_setup = sh7757lcr_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .mv_init_irq = init_sh7757lcr_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .mv_mode_pins = sh7757lcr_mode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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