Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * June 2006 Steve Glendinning <steve.glendinning@shawell.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Polaris-specific resource declaration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/heartbeat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <cpu/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <mach-se/mach/se.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define BCR2		(0xFFFFFF62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define WCR2		(0xFFFFFF66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AREA5_WAIT_CTRL	(0x1C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define WAIT_STATES_10	(0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Dummy supplies, where voltage doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static struct regulator_consumer_supply dummy_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static struct resource smsc911x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.name		= "smsc911x-memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.start		= PA_EXT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.end		= PA_EXT5 + 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.flags		= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.name		= "smsc911x-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.start		= IRQ0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.end		= IRQ0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.flags		= IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct smsc911x_platform_config smsc911x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.flags		= SMSC911X_USE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.phy_interface	= PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct platform_device smsc911x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.name		= "smsc911x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.id		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.num_resources	= ARRAY_SIZE(smsc911x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.resource	= smsc911x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.platform_data = &smsc911x_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct heartbeat_data heartbeat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.bit_pos	= heartbeat_bit_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.nr_bits	= ARRAY_SIZE(heartbeat_bit_pos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct resource heartbeat_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.start	= PORT_PCDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.end	= PORT_PCDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct platform_device heartbeat_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.name		= "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.dev	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.platform_data	= &heartbeat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.num_resources	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.resource	= &heartbeat_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static struct platform_device *polaris_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	&smsc911x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	&heartbeat_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int __init polaris_initialise(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u16 wcr, bcr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	printk(KERN_INFO "Configuring Polaris external bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* Configure area 5 with 2 wait states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	wcr = __raw_readw(WCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	wcr &= (~AREA5_WAIT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	wcr |= (WAIT_STATES_10 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	__raw_writew(wcr, WCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Configure area 5 for 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	bcr_mask = __raw_readw(BCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	bcr_mask |= 1 << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__raw_writew(bcr_mask, BCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return platform_add_devices(polaris_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				    ARRAY_SIZE(polaris_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) arch_initcall(polaris_initialise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct ipr_data ipr_irq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* External IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ IRQ0_IRQ, 0,  0,  1, },	/* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ IRQ1_IRQ, 0,  4,  1, },	/* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static unsigned long ipr_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	INTC_IPRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct ipr_desc ipr_irq_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.ipr_offsets	= ipr_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.nr_offsets	= ARRAY_SIZE(ipr_offsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.ipr_data	= ipr_irq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.nr_irqs	= ARRAY_SIZE(ipr_irq_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.name	= "sh7709-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void __init init_polaris_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	__raw_writew(0, BCR_ILCRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__raw_writew(0, BCR_ILCRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	__raw_writew(0, BCR_ILCRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	__raw_writew(0, BCR_ILCRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	__raw_writew(0, BCR_ILCRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	__raw_writew(0, BCR_ILCRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	__raw_writew(0, BCR_ILCRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	register_ipr_controller(&ipr_irq_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct sh_machine_vector mv_polaris __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.mv_name		= "Polaris",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.mv_init_irq		= init_polaris_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };