^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/sh/boards/magicpanel/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Markus Brunner, Mark Jonas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Magic Panel Release 2 board setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <mach/magicpanelr2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/heartbeat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <cpu/sh7720.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Dummy supplies, where voltage doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct regulator_consumer_supply dummy_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) REGULATOR_SUPPLY("vddvario", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) REGULATOR_SUPPLY("vdd33a", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Wait until reset finished. Timeout is 100ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int __init ethernet_reset_finished(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (LAN9115_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (i = 0; i < 10; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (LAN9115_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __init reset_ethernet(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* PMDR: LAN_RESET=on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CLRBITS_OUTB(0x10, PORT_PMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* PMDR: LAN_RESET=off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SETBITS_OUTB(0x10, PORT_PMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void __init setup_chip_select(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* CS2: LAN (0x08000000 - 0x0bffffff) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* no idle cycles, normal space, 8 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writel(0x36db0400, CS2BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* (SW:1.5 WR:3 HW:1.5), ext. wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __raw_writel(0x000003c0, CS2WCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* no idle cycles, normal space, 8 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __raw_writel(0x00000200, CS4BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* (SW:1.5 WR:3 HW:1.5), ext. wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __raw_writel(0x00100981, CS4WCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* no idle cycles, normal space, 8 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __raw_writel(0x00000200, CS5ABCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* (SW:1.5 WR:3 HW:1.5), ext. wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __raw_writel(0x00100981, CS5AWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* no idle cycles, normal space, 8 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __raw_writel(0x00000200, CS5BBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* (SW:1.5 WR:3 HW:1.5), ext. wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __raw_writel(0x00100981, CS5BWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* no idle cycles, normal space, 8 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writel(0x00000200, CS6ABCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writel(0x001009C1, CS6AWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void __init setup_port_multiplexing(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* K7 (x); K6 (x); K5 (x); K4 (x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * L3 TCK; L2 (x); L1 (x); L0 (x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * M1 CS5B(CAN3_CS); M0 GPI+(nc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * LAN_RESET=off, BUZZER=off, LCD_BL=off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __raw_writeb(0x30, PORT_PMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __raw_writeb(0xF0, PORT_PMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #error Unknown revision of PLATFORM_MP_R2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* P7 (x); P6 (x); P5 (x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __raw_writeb(0x10, PORT_PPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* R7 A25; R6 A24; R5 A23; R4 A22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * R3 A21; R2 A20; R1 A19; R0 A0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) gpio_request(GPIO_FN_A25, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gpio_request(GPIO_FN_A24, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) gpio_request(GPIO_FN_A23, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpio_request(GPIO_FN_A22, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) gpio_request(GPIO_FN_A21, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gpio_request(GPIO_FN_A20, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) gpio_request(GPIO_FN_A19, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) gpio_request(GPIO_FN_A0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void __init mpr2_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* set Pin Select Register A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __raw_writew(0xAABC, PORT_PSELA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* set Pin Select Register B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __raw_writew(0x3C00, PORT_PSELB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* set Pin Select Register C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __raw_writew(0x0000, PORT_PSELC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __raw_writew(0x0000, PORT_PSELD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __raw_writew(0x0101, PORT_UTRCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __raw_writew(0xA5C0, PORT_UCLKCR_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) setup_chip_select();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) setup_port_multiplexing();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reset_ethernet();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CONFIG_SH_MAGIC_PANEL_R2_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ethernet_reset_finished() == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) printk(KERN_WARNING "Ethernet not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct resource smsc911x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .start = 0xa8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .end = 0xabffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .start = evt2irq(0x660),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .end = evt2irq(0x660),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct smsc911x_platform_config smsc911x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .phy_interface = PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .flags = SMSC911X_USE_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_device smsc911x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "smsc911x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_resources = ARRAY_SIZE(smsc911x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .resource = smsc911x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .platform_data = &smsc911x_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct resource heartbeat_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .start = PA_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .end = PA_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct heartbeat_data heartbeat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .flags = HEARTBEAT_INVERTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct platform_device heartbeat_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .platform_data = &heartbeat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_resources = ARRAY_SIZE(heartbeat_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .resource = heartbeat_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct mtd_partition mpr2_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Reserved for bootloader, read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "Bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .offset = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .size = MPR2_MTD_BOOTLOADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Reserved for kernel image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = "Kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .offset = MTDPART_OFS_NXTBLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .size = MPR2_MTD_KERNEL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Rest is used for Flash FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .name = "Flash_FS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .offset = MTDPART_OFS_NXTBLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct physmap_flash_data flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parts = mpr2_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .nr_parts = ARRAY_SIZE(mpr2_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct resource flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .start = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .end = 0x2000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct platform_device flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .resource = &flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .platform_data = &flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Add all resources to the platform_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct platform_device *mpr2_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &heartbeat_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &smsc911x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int __init mpr2_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) device_initcall(mpr2_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Initialize IRQ setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void __init init_mpr2_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * The Machine Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct sh_machine_vector mv_mpr2 __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .mv_name = "mpr2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .mv_setup = mpr2_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .mv_init_irq = init_mpr2_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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