^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALPHAPROJECT AP-SH4A-3A Support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Yoshihiro Shimoda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/smsc911x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct mtd_partition nor_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .name = "loader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .offset = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .size = 512 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "bootenv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .size = 512 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .size = 4 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .name = "data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct physmap_flash_data nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .parts = nor_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .nr_parts = ARRAY_SIZE(nor_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct resource nor_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .start = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .end = 0x01000000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct platform_device nor_flash_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .platform_data = &nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .num_resources = ARRAY_SIZE(nor_flash_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .resource = nor_flash_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Dummy supplies, where voltage doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct regulator_consumer_supply dummy_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) REGULATOR_SUPPLY("vddvario", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) REGULATOR_SUPPLY("vdd33a", "smsc911x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct resource smsc911x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .name = "smsc911x-memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .start = 0xA4000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .end = 0xA4000000 + SZ_256 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "smsc911x-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .start = evt2irq(0x200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .end = evt2irq(0x200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct smsc911x_platform_config smsc911x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = SMSC911X_USE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .phy_interface = PHY_INTERFACE_MODE_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct platform_device smsc911x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = "smsc911x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .num_resources = ARRAY_SIZE(smsc911x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .resource = smsc911x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .platform_data = &smsc911x_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct platform_device *apsh4a3a_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) &nor_flash_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &smsc911x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int __init apsh4a3a_devices_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return platform_add_devices(apsh4a3a_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ARRAY_SIZE(apsh4a3a_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) device_initcall(apsh4a3a_devices_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int apsh4a3a_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk = clk_get(NULL, "extal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = clk_set_rate(clk, 33333000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Initialize the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void __init apsh4a3a_setup(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void __init apsh4a3a_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) plat_irq_setup_pins(IRQ_MODE_IRQ7654);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Return the board specific boot mode pin configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int apsh4a3a_mode_pins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* These are the factory default settings of SW1 and SW2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * If you change these dip switches then you will need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * adjust the values below as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) value &= ~MODE_PIN0; /* Clock Mode 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) value &= ~MODE_PIN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) value &= ~MODE_PIN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) value &= ~MODE_PIN3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) value |= MODE_PIN4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) value &= ~MODE_PIN5; /* 16-bit Area0 bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) value |= MODE_PIN6; /* Area 0 SRAM interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) value |= MODE_PIN7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) value |= MODE_PIN8; /* Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) value |= MODE_PIN9; /* Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) value |= MODE_PIN10; /* Crystal resonator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) value |= MODE_PIN11; /* Display Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) value |= MODE_PIN12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) value &= ~MODE_PIN13; /* 29-bit address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) value |= MODE_PIN14; /* No PLL step-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * The Machine Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct sh_machine_vector mv_apsh4a3a __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .mv_name = "AP-SH4A-3A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .mv_setup = apsh4a3a_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .mv_clk_init = apsh4a3a_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .mv_init_irq = apsh4a3a_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mv_mode_pins = apsh4a3a_mode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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