Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

3 Commits   0 Branches   0 Tags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) menu "Processor features"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 	prompt "Endianness selection" 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	default CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	  Some SuperH machines can be configured for either little or big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	  endian byte order. These modes require different kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) config CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	bool "Little Endian"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) config CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	bool "Big Endian"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) config SH_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	prompt "FPU support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	depends on CPU_HAS_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	  Selecting this option will enable support for SH processors that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	  have FPU units (ie, SH77xx).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	  This option must be set in order to enable the FPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) config SH_FPU_EMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	prompt "FPU emulation support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	depends on !SH_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	  Selecting this option will enable support for software FPU emulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	  Most SH-3 users will want to say Y here, whereas most SH-4 users will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	  want to say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) config SH_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	prompt "DSP support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	depends on CPU_HAS_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	  Selecting this option will enable support for SH processors that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	  have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	  This option must be set in order to enable the DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) config SH_ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	prompt "ADC support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	depends on CPU_SH3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  Selecting this option will allow the Linux kernel to use SH3 on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	  ADC module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	  If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) config SH_STORE_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	bool "Support for Store Queues"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	depends on CPU_SH4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	  Selecting this option will enable an in-kernel API for manipulating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	  the store queues integrated in the SH-4 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) config SPECULATIVE_EXECUTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	bool "Speculative subroutine return"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	  This enables support for a speculative instruction fetch for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	  subroutine return. There are various pitfalls associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	  this, as outlined in the SH7780 hardware manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	  If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) config CPU_HAS_INTEVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) config CPU_HAS_IPR_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) config CPU_HAS_SR_RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	  This will enable the use of SR.RB register bank usage. Processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	  that are lacking this bit must have another method in place for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	  accomplishing what is taken care of by the banked registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	  See <file:Documentation/sh/register-banks.rst> for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	  information on SR.RB and register banking in the kernel in general.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) config CPU_HAS_PTEAEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) config CPU_HAS_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) config CPU_HAS_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) endmenu