^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define KMSG_COMPONENT "zpci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/isc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/airq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static enum {FLOATING, DIRECTED} irq_delivery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SIC_IRQ_MODE_ALL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIC_IRQ_MODE_SINGLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIC_IRQ_MODE_DIRECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIC_IRQ_MODE_D_ALL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIC_IRQ_MODE_D_SINGLE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIC_IRQ_MODE_SET_CPU 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * summary bit vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * FLOATING - summary bit per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * DIRECTED - summary bit per cpu (only used in fallback path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct airq_iv *zpci_sbv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * interrupt bit vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * FLOATING - interrupt bit vector per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DIRECTED - interrupt bit vector per cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct airq_iv **zpci_ibv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Modify PCI: Register adapter interruptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int zpci_set_airq(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct zpci_fib fib = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) fib.fmt0.isc = PCI_ISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) fib.fmt0.sum = 1; /* enable summary notifications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) fib.fmt0.noi = airq_iv_end(zdev->aibv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) fib.fmt0.aibv = (unsigned long) zdev->aibv->vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) fib.fmt0.aibvo = 0; /* each zdev has its own interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) fib.fmt0.aisb = (unsigned long) zpci_sbv->vector + (zdev->aisb/64)*8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) fib.fmt0.aisbo = zdev->aisb & 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Modify PCI: Unregister adapter interruptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int zpci_clear_airq(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct zpci_fib fib = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 cc, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cc = zpci_mod_fc(req, &fib, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (cc == 3 || (cc == 1 && status == 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Function already gone or IRQs already deregistered. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) cc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return cc ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Modify PCI: Register CPU directed interruptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int zpci_set_directed_irq(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct zpci_fib fib = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) fib.fmt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) fib.fmt1.noi = zdev->msi_nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) fib.fmt1.dibvo = zdev->msi_first_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Modify PCI: Unregister CPU directed interruptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int zpci_clear_directed_irq(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct zpci_fib fib = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 cc, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) fib.fmt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cc = zpci_mod_fc(req, &fib, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (cc == 3 || (cc == 1 && status == 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Function already gone or IRQs already deregistered. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) cc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return cc ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int zpci_set_irq_affinity(struct irq_data *data, const struct cpumask *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct msi_desc *entry = irq_get_msi_desc(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct msi_msg msg = entry->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int cpu_addr = smp_cpu_get_cpu_address(cpumask_first(dest));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msg.address_lo &= 0xff0000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) msg.address_lo |= (cpu_addr << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pci_write_msi_msg(data->irq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct irq_chip zpci_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "PCI-MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .irq_mask = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void zpci_handle_cpu_local_irq(bool rescan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct airq_iv *dibv = zpci_ibv[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int irqs_on = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (bit = 0;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Scan the directed IRQ bit vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bit = airq_iv_scan(dibv, bit, airq_iv_end(dibv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (bit == -1UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!rescan || irqs_on++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* End of second scan with interrupts on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* First scan complete, reenable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) inc_irq_stat(IRQIO_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) generic_handle_irq(airq_iv_get_data(dibv, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct cpu_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) call_single_data_t csd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) atomic_t scheduled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_irq_data, irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void zpci_handle_remote_irq(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) atomic_t *scheduled = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) zpci_handle_cpu_local_irq(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } while (atomic_dec_return(scheduled));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void zpci_handle_fallback_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct cpu_irq_data *cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int irqs_on = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) for (cpu = 0;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cpu = airq_iv_scan(zpci_sbv, cpu, airq_iv_end(zpci_sbv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (cpu == -1UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (irqs_on++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* End of second scan with interrupts on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* First scan complete, reenable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cpu_data = &per_cpu(irq_data, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (atomic_inc_return(&cpu_data->scheduled) > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cpu_data->csd.func = zpci_handle_remote_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cpu_data->csd.info = &cpu_data->scheduled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cpu_data->csd.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) smp_call_function_single_async(cpu, &cpu_data->csd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void zpci_directed_irq_handler(struct airq_struct *airq, bool floating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (floating) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) inc_irq_stat(IRQIO_PCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) zpci_handle_fallback_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) inc_irq_stat(IRQIO_PCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) zpci_handle_cpu_local_irq(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void zpci_floating_irq_handler(struct airq_struct *airq, bool floating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long si, ai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct airq_iv *aibv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int irqs_on = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) inc_irq_stat(IRQIO_PCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for (si = 0;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Scan adapter summary indicator bit vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) si = airq_iv_scan(zpci_sbv, si, airq_iv_end(zpci_sbv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (si == -1UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (irqs_on++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* End of second scan with interrupts on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* First scan complete, reenable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) si = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Scan the adapter interrupt vector for this device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) aibv = zpci_ibv[si];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (ai = 0;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ai == -1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) inc_irq_stat(IRQIO_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) airq_iv_lock(aibv, ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) generic_handle_irq(airq_iv_get_data(aibv, ai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) airq_iv_unlock(aibv, ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct zpci_dev *zdev = to_zpci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int hwirq, msi_vecs, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct msi_desc *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int rc, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) zdev->aisb = -1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) zdev->msi_first_bit = -1U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (type == PCI_CAP_ID_MSI && nvec > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (irq_delivery == DIRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Allocate cpu vector bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bit = airq_iv_alloc(zpci_ibv[0], msi_vecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (bit == -1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Allocate adapter summary indicator bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bit = airq_iv_alloc_bit(zpci_sbv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (bit == -1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) zdev->aisb = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Create adapter interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!zdev->aibv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Wire up shortcut pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) zpci_ibv[bit] = zdev->aibv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Each function has its own interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Request MSI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hwirq = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for_each_pci_msi_entry(msi, pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (hwirq - bit >= msi_vecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) irq = __irq_alloc_descs(-1, 0, 1, 0, THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (irq_delivery == DIRECTED) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msi->affinity : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rc = irq_set_msi_desc(irq, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) irq_set_chip_and_handler(irq, &zpci_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) handle_percpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) msg.data = hwirq - bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (irq_delivery == DIRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (msi->affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cpu = cpumask_first(&msi->affinity->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cpu_addr = smp_cpu_get_cpu_address(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) msg.address_lo = zdev->msi_addr & 0xff0000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) msg.address_lo |= (cpu_addr << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) airq_iv_set_data(zpci_ibv[cpu], hwirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) msg.address_lo = zdev->msi_addr & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) airq_iv_set_data(zdev->aibv, hwirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) msg.address_hi = zdev->msi_addr >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pci_write_msi_msg(irq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hwirq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) zdev->msi_first_bit = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) zdev->msi_nr_irqs = msi_vecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (irq_delivery == DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rc = zpci_set_directed_irq(zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rc = zpci_set_airq(zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return (msi_vecs == nvec) ? 0 : msi_vecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void arch_teardown_msi_irqs(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct zpci_dev *zdev = to_zpci(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct msi_desc *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (irq_delivery == DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) rc = zpci_clear_directed_irq(zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rc = zpci_clear_airq(zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Release MSI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for_each_pci_msi_entry(msi, pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!msi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (msi->msi_attrib.is_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __pci_msix_desc_mask_irq(msi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __pci_msi_desc_mask_irq(msi, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) irq_set_msi_desc(msi->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) irq_free_desc(msi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) msi->msg.address_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) msi->msg.address_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) msi->msg.data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) msi->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (zdev->aisb != -1UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) zpci_ibv[zdev->aisb] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) airq_iv_free_bit(zpci_sbv, zdev->aisb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) zdev->aisb = -1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (zdev->aibv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) airq_iv_release(zdev->aibv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) zdev->aibv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if ((irq_delivery == DIRECTED) && zdev->msi_first_bit != -1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct airq_struct zpci_airq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .handler = zpci_floating_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .isc = PCI_ISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void __init cpu_enable_directed_irq(void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) union zpci_sic_iib iib = {{0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) iib.cdiib.dibv_addr = (u64) zpci_ibv[smp_processor_id()]->vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __zpci_set_irq_ctrl(SIC_IRQ_MODE_SET_CPU, 0, &iib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int __init zpci_directed_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) union zpci_sic_iib iib = {{0}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) zpci_sbv = airq_iv_create(num_possible_cpus(), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!zpci_sbv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) iib.diib.isc = PCI_ISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) iib.diib.nr_cpus = num_possible_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) iib.diib.disb_addr = (u64) zpci_sbv->vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!zpci_ibv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Per CPU IRQ vectors look the same but bit-allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * is only done on the first vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) AIRQ_IV_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) AIRQ_IV_CACHELINE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (!cpu ? AIRQ_IV_ALLOC : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!zpci_ibv[cpu])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) on_each_cpu(cpu_enable_directed_irq, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) zpci_irq_chip.irq_set_affinity = zpci_set_irq_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int __init zpci_floating_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!zpci_ibv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!zpci_sbv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) kfree(zpci_ibv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int __init zpci_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) irq_delivery = sclp.has_dirq ? DIRECTED : FLOATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (s390_pci_force_floating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) irq_delivery = FLOATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (irq_delivery == DIRECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) zpci_airq.handler = zpci_directed_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) rc = register_adapter_interrupt(&zpci_airq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Set summary to 1 to be called every time for the ISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *zpci_airq.lsi_ptr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (irq_delivery) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case FLOATING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rc = zpci_floating_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case DIRECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rc = zpci_directed_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto out_airq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Enable floating IRQs (with suppression after one IRQ). When using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * directed IRQs this enables the fallback path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) out_airq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unregister_adapter_interrupt(&zpci_airq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void __init zpci_irq_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (irq_delivery == DIRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) airq_iv_release(zpci_ibv[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) kfree(zpci_ibv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (zpci_sbv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) airq_iv_release(zpci_sbv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unregister_adapter_interrupt(&zpci_airq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags