^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * s390 specific pci instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright IBM Corp. 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/jump_label.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/facility.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/pci_insn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/pci_debug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pci_io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u64 req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } __packed data = {req, offset, cc, status};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) zpci_err_hex(&data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Modify PCI Function Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) " .insn rxy,0xe300000000d0,%[req],%[fib]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) " ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) : : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *status = req >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cc = __mpcifc(req, fib, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (cc == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) msleep(ZPCI_INSN_BUSY_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } while (cc == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) zpci_err_insn(cc, *status, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Refresh PCI Translations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) register u64 __addr asm("2") = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) register u64 __range asm("3") = range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) " .insn rre,0xb9d30000,%[fn],%[addr]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) " ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) : [cc] "=d" (cc), [fn] "+d" (fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) : [addr] "d" (__addr), "d" (__range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *status = fn >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 cc, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cc = __rpcit(fn, addr, range, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (cc == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) udelay(ZPCI_INSN_BUSY_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } while (cc == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) zpci_err_insn(cc, status, addr, range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (cc == 1 && (status == 4 || status == 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return (cc) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Set Interruption Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!test_facility(72))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* PCI Load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) register u64 __req asm("2") = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) register u64 __offset asm("3") = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int cc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u64 __data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) " .insn rre,0xb9d20000,%[data],%[req]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "0: ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EX_TABLE(0b, 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) : "d" (__offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *status = __req >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *data = __data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 __data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cc = ____pcilg(&__data, req, offset, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *data = __data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int __zpci_load(u64 *data, u64 req, u64 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cc = __pcilg(data, req, offset, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (cc == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) udelay(ZPCI_INSN_BUSY_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } while (cc == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) zpci_err_insn(cc, status, req, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return (cc > 0) ? -EIO : cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EXPORT_SYMBOL_GPL(__zpci_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return __zpci_load(data, req, ZPCI_OFFSET(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) register u64 addr asm("2") = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) register u64 r3 asm("3") = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int cc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u64 __data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) " .insn rre,0xb9d60000,%[data],%[ioaddr]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "0: ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) EX_TABLE(0b, 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) : [cc] "+d" (cc), [data] "=d" (__data), "+d" (r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) : [ioaddr] "d" (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *status = r3 >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *data = __data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!static_branch_unlikely(&have_mio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return zpci_load_fh(data, addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cc = __pcilg_mio(data, (__force u64) addr, len, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) zpci_err_insn(cc, status, 0, (__force u64) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return (cc > 0) ? -EIO : cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EXPORT_SYMBOL_GPL(zpci_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* PCI Store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) register u64 __req asm("2") = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) register u64 __offset asm("3") = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int cc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) " .insn rre,0xb9d00000,%[data],%[req]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "0: ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) EX_TABLE(0b, 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) : [cc] "+d" (cc), [req] "+d" (__req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) : "d" (__offset), [data] "d" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *status = __req >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int __zpci_store(u64 data, u64 req, u64 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cc = __pcistg(data, req, offset, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (cc == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) udelay(ZPCI_INSN_BUSY_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } while (cc == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) zpci_err_insn(cc, status, req, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return (cc > 0) ? -EIO : cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EXPORT_SYMBOL_GPL(__zpci_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return __zpci_store(data, req, ZPCI_OFFSET(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) register u64 addr asm("2") = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) register u64 r3 asm("3") = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int cc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) " .insn rre,0xb9d40000,%[data],%[ioaddr]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "0: ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) EX_TABLE(0b, 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) : [cc] "+d" (cc), "+d" (r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) : [data] "d" (data), [ioaddr] "d" (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *status = r3 >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!static_branch_unlikely(&have_mio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return zpci_store_fh(addr, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cc = __pcistg_mio(data, (__force u64) addr, len, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) zpci_err_insn(cc, status, 0, (__force u64) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return (cc > 0) ? -EIO : cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) EXPORT_SYMBOL_GPL(zpci_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* PCI Store Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int cc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "0: ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) EX_TABLE(0b, 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) : [cc] "+d" (cc), [req] "+d" (req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) : [offset] "d" (offset), [data] "Q" (*data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *status = req >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int __zpci_store_block(const u64 *data, u64 req, u64 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cc = __pcistb(data, req, offset, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (cc == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) udelay(ZPCI_INSN_BUSY_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } while (cc == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) zpci_err_insn(cc, status, req, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return (cc > 0) ? -EIO : cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) EXPORT_SYMBOL_GPL(__zpci_store_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static inline int zpci_write_block_fh(volatile void __iomem *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const void *src, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u64 offset = ZPCI_OFFSET(dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return __zpci_store_block(src, req, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int cc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) " .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "0: ipm %[cc]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) " srl %[cc],28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "1:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) EX_TABLE(0b, 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) : [cc] "+d" (cc), [len] "+d" (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) : [ioaddr] "d" (ioaddr), [data] "Q" (*data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *status = len >> 24 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int zpci_write_block(volatile void __iomem *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) const void *src, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!static_branch_unlikely(&have_mio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return zpci_write_block_fh(dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cc = __pcistb_mio(src, (__force u64) dst, len, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) zpci_err_insn(cc, status, 0, (__force u64) dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return (cc > 0) ? -EIO : cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) EXPORT_SYMBOL_GPL(zpci_write_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline void __pciwb_mio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long unused = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) asm volatile (".insn rre,0xb9d50000,%[op],%[op]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) : [op] "+d" (unused));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void zpci_barrier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (static_branch_likely(&have_mio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __pciwb_mio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) EXPORT_SYMBOL_GPL(zpci_barrier);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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