^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright IBM Corp. 2004, 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Thomas Spatzier <tspat@de.ibm.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file contains interrupt related functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/profile.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ftrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/irq_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cputime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/lowcore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/stacktrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "entry.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct irq_class {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The list of "main" irq classes on s390. This is the list of interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Historically only external and I/O interrupts have been part of /proc/stat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * We can't add the split external and I/O sub classes since the first field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * in the "intr" line in /proc/stat is supposed to be the sum of all other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Since the external and I/O interrupt fields are already sums we would end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * up with having a sum which accounts each interrupt twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {.irq = EXT_INTERRUPT, .name = "EXT"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {.irq = IO_INTERRUPT, .name = "I/O"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {.irq = THIN_INTERRUPT, .name = "AIO"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The list of split external and I/O interrupts that appear only in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * /proc/interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * In addition this list contains non external / I/O events like NMIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct irq_class irqclass_sub_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void do_IRQ(struct pt_regs *regs, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pt_regs *old_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (tod_after_eq(S390_lowcore.int_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) S390_lowcore.clock_comparator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Serve timer interrupts first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clock_comparator_work();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void show_msi_interrupt(struct seq_file *p, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct irq_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) irq_lock_sparse();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) desc = irq_to_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) seq_printf(p, "%3d: ", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for_each_online_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (desc->irq_data.chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) seq_printf(p, " %8s", desc->irq_data.chip->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (desc->action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) seq_printf(p, " %s", desc->action->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) seq_putc(p, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) irq_unlock_sparse();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * show_interrupts is needed by /proc/interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int show_interrupts(struct seq_file *p, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int index = *(loff_t *) v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int cpu, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) get_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) seq_puts(p, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for_each_online_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) seq_printf(p, "CPU%-8d", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) seq_putc(p, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (index < NR_IRQS_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) seq_printf(p, "%s: ", irqclass_main_desc[index].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) irq = irqclass_main_desc[index].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) for_each_online_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) seq_putc(p, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (index < nr_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) show_msi_interrupt(p, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (index = 0; index < NR_ARCH_IRQS; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) irq = irqclass_sub_desc[index].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for_each_online_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) seq_printf(p, "%10u ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) per_cpu(irq_stat, cpu).irqs[irq]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (irqclass_sub_desc[index].desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) seq_printf(p, " %s", irqclass_sub_desc[index].desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) seq_putc(p, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) put_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int arch_dynirq_lower_bound(unsigned int from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Switch to the asynchronous interrupt stack for softirq execution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void do_softirq_own_stack(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) old = current_stack_pointer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Check against async. stack address range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) new = S390_lowcore.async_stack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CALL_ON_STACK(__do_softirq, new, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* We are already on the async stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __do_softirq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * ext_int_hash[index] is the list head for all external interrupts that hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * to this index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct ext_int_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ext_int_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct hlist_node entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct rcu_head rcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* ext_int_hash_lock protects the handler lists for external interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static DEFINE_SPINLOCK(ext_int_hash_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline int ext_hash(u16 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int register_external_irq(u16 code, ext_int_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct ext_int_info *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) p = kmalloc(sizeof(*p), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) p->code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) p->handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) index = ext_hash(code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_lock_irqsave(&ext_int_hash_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spin_unlock_irqrestore(&ext_int_hash_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EXPORT_SYMBOL(register_external_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int unregister_external_irq(u16 code, ext_int_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct ext_int_info *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int index = ext_hash(code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_lock_irqsave(&ext_int_hash_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (p->code == code && p->handler == handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) hlist_del_rcu(&p->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) kfree_rcu(p, rcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) spin_unlock_irqrestore(&ext_int_hash_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXPORT_SYMBOL(unregister_external_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static irqreturn_t do_ext_interrupt(int irq, void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct pt_regs *regs = get_irq_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct ext_code ext_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct ext_int_info *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ext_code = *(struct ext_code *) ®s->int_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ext_code.code != EXT_IRQ_CLK_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) set_cpu_flag(CIF_NOHZ_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) index = ext_hash(ext_code.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (unlikely(p->code != ext_code.code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) p->handler(ext_code, regs->int_parm, regs->int_parm_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void __init init_ext_interrupts(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) INIT_HLIST_HEAD(&ext_int_hash[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) irq_set_chip_and_handler(EXT_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) &dummy_irq_chip, handle_percpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) panic("Failed to register EXT interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) init_cio_interrupts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) init_airq_interrupts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) init_ext_interrupts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static DEFINE_SPINLOCK(irq_subclass_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static unsigned char irq_subclass_refcount[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void irq_subclass_register(enum irq_subclass subclass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_lock(&irq_subclass_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!irq_subclass_refcount[subclass])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ctl_set_bit(0, subclass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) irq_subclass_refcount[subclass]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) spin_unlock(&irq_subclass_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) EXPORT_SYMBOL(irq_subclass_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void irq_subclass_unregister(enum irq_subclass subclass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock(&irq_subclass_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) irq_subclass_refcount[subclass]--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!irq_subclass_refcount[subclass])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ctl_clear_bit(0, subclass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spin_unlock(&irq_subclass_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL(irq_subclass_unregister);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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