Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __S390_ASM_SIGP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __S390_ASM_SIGP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* SIGP order codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define SIGP_SENSE		      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define SIGP_EXTERNAL_CALL	      2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define SIGP_EMERGENCY_SIGNAL	      3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SIGP_START		      4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SIGP_STOP		      5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SIGP_RESTART		      6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SIGP_STOP_AND_STORE_STATUS    9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SIGP_INITIAL_CPU_RESET	     11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SIGP_CPU_RESET		     12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SIGP_SET_PREFIX		     13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SIGP_STORE_STATUS_AT_ADDRESS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SIGP_SET_ARCHITECTURE	     18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIGP_COND_EMERGENCY_SIGNAL   19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIGP_SENSE_RUNNING	     21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIGP_SET_MULTI_THREADING     22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIGP_STORE_ADDITIONAL_STATUS 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* SIGP condition codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIGP_CC_ORDER_CODE_ACCEPTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIGP_CC_STATUS_STORED	    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIGP_CC_BUSY		    2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIGP_CC_NOT_OPERATIONAL	    3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SIGP cpu status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIGP_STATUS_INVALID_ORDER	0x00000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIGP_STATUS_CHECK_STOP		0x00000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIGP_STATUS_STOPPED		0x00000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIGP_STATUS_EXT_CALL_PENDING	0x00000080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIGP_STATUS_INVALID_PARAMETER	0x00000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIGP_STATUS_INCORRECT_STATE	0x00000200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIGP_STATUS_NOT_RUNNING		0x00000400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline int ____pcpu_sigp(u16 addr, u8 order, unsigned long parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	register unsigned long reg1 asm ("1") = parm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		"	sigp	%1,%2,0(%3)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		"	ipm	%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		"	srl	%0,28\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		: "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	*status = reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline int __pcpu_sigp(u16 addr, u8 order, unsigned long parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			      u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u32 _status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	int cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	cc = ____pcpu_sigp(addr, order, parm, &_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	if (status && cc == SIGP_CC_STATUS_STORED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		*status = _status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	return cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* __S390_ASM_SIGP_H */