^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * S390 version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright IBM Corp. 1999, 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _ASM_S390_SETUP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _ASM_S390_SETUP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <uapi/asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/build_bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define EP_OFFSET 0x10008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EP_STRING "S390EP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PARMAREA 0x10400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EARLY_SCCB_OFFSET 0x11000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HEAD_END 0x12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EARLY_SCCB_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Machine features detected in early.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MACHINE_FLAG_VM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MACHINE_FLAG_KVM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MACHINE_FLAG_LPAR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MACHINE_FLAG_DIAG9C BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MACHINE_FLAG_ESOP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MACHINE_FLAG_IDTE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MACHINE_FLAG_EDAT1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MACHINE_FLAG_EDAT2 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MACHINE_FLAG_TOPOLOGY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MACHINE_FLAG_TE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MACHINE_FLAG_TLB_LC BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MACHINE_FLAG_VX BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MACHINE_FLAG_TLB_GUEST BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MACHINE_FLAG_NX BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MACHINE_FLAG_GS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MACHINE_FLAG_SCC BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MACHINE_FLAG_PCI_MIO BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPP_MAGIC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPP_PID_MASK _AC(0xffffffff, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Offsets to entry points in kernel/head.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STARTUP_NORMAL_OFFSET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STARTUP_KDUMP_OFFSET 0x10010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Offsets to parameters in kernel/head.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IPL_DEVICE_OFFSET 0x10400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define INITRD_START_OFFSET 0x10408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define INITRD_SIZE_OFFSET 0x10410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OLDMEM_BASE_OFFSET 0x10418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OLDMEM_SIZE_OFFSET 0x10420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define KERNEL_VERSION_OFFSET 0x10428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define COMMAND_LINE_OFFSET 0x10480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <asm/lowcore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IPL_DEVICE (*(unsigned long *) (IPL_DEVICE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define INITRD_START (*(unsigned long *) (INITRD_START_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define INITRD_SIZE (*(unsigned long *) (INITRD_SIZE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OLDMEM_BASE (*(unsigned long *) (OLDMEM_BASE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OLDMEM_SIZE (*(unsigned long *) (OLDMEM_SIZE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define COMMAND_LINE ((char *) (COMMAND_LINE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct parmarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long ipl_device; /* 0x10400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long initrd_start; /* 0x10408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long initrd_size; /* 0x10410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long oldmem_base; /* 0x10418 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long oldmem_size; /* 0x10420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long kernel_version; /* 0x10428 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) char pad1[0x10480 - 0x10430]; /* 0x10430 - 0x10480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) char command_line[ARCH_COMMAND_LINE_SIZE]; /* 0x10480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern unsigned int zlib_dfltcc_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ZLIB_DFLTCC_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ZLIB_DFLTCC_FULL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ZLIB_DFLTCC_DEFLATE_ONLY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ZLIB_DFLTCC_INFLATE_ONLY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ZLIB_DFLTCC_FULL_DEBUG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern int noexec_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern int memory_end_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern unsigned long memory_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern unsigned long vmalloc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern unsigned long max_physmem_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* The Write Back bit position in the physaddr is given by the SLPC PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extern unsigned long mio_wb_bit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MACHINE_IS_VM (S390_lowcore.machine_flags & MACHINE_FLAG_VM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MACHINE_IS_KVM (S390_lowcore.machine_flags & MACHINE_FLAG_KVM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MACHINE_IS_LPAR (S390_lowcore.machine_flags & MACHINE_FLAG_LPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MACHINE_HAS_DIAG9C (S390_lowcore.machine_flags & MACHINE_FLAG_DIAG9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MACHINE_HAS_ESOP (S390_lowcore.machine_flags & MACHINE_FLAG_ESOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MACHINE_HAS_IDTE (S390_lowcore.machine_flags & MACHINE_FLAG_IDTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MACHINE_HAS_EDAT1 (S390_lowcore.machine_flags & MACHINE_FLAG_EDAT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MACHINE_HAS_EDAT2 (S390_lowcore.machine_flags & MACHINE_FLAG_EDAT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MACHINE_HAS_TOPOLOGY (S390_lowcore.machine_flags & MACHINE_FLAG_TOPOLOGY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MACHINE_HAS_TE (S390_lowcore.machine_flags & MACHINE_FLAG_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MACHINE_HAS_TLB_LC (S390_lowcore.machine_flags & MACHINE_FLAG_TLB_LC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MACHINE_HAS_VX (S390_lowcore.machine_flags & MACHINE_FLAG_VX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MACHINE_HAS_TLB_GUEST (S390_lowcore.machine_flags & MACHINE_FLAG_TLB_GUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MACHINE_HAS_NX (S390_lowcore.machine_flags & MACHINE_FLAG_NX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MACHINE_HAS_GS (S390_lowcore.machine_flags & MACHINE_FLAG_GS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MACHINE_HAS_SCC (S390_lowcore.machine_flags & MACHINE_FLAG_SCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MACHINE_HAS_PCI_MIO (S390_lowcore.machine_flags & MACHINE_FLAG_PCI_MIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Console mode. Override with conmode=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) extern unsigned int console_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern unsigned int console_devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern unsigned int console_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CONSOLE_IS_UNDEFINED (console_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CONSOLE_IS_SCLP (console_mode == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CONSOLE_IS_3215 (console_mode == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CONSOLE_IS_3270 (console_mode == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CONSOLE_IS_VT220 (console_mode == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CONSOLE_IS_HVC (console_mode == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SET_CONSOLE_SCLP do { console_mode = 1; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SET_CONSOLE_3215 do { console_mode = 2; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SET_CONSOLE_3270 do { console_mode = 3; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SET_CONSOLE_VT220 do { console_mode = 4; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SET_CONSOLE_HVC do { console_mode = 5; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef CONFIG_PFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern int pfault_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern void pfault_fini(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #else /* CONFIG_PFAULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define pfault_init() ({-1;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define pfault_fini() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* CONFIG_PFAULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #ifdef CONFIG_VMCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void vmcp_cma_reserve(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline void vmcp_cma_reserve(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void report_user_fault(struct pt_regs *regs, long signr, int is_mm_fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void cmma_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void cmma_init_nodat(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern void (*_machine_restart)(char *command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) extern void (*_machine_halt)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) extern void (*_machine_power_off)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern unsigned long __kaslr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline unsigned long kaslr_offset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return __kaslr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline u32 gen_lpswe(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) BUILD_BUG_ON(addr > 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0xb2b20000 | addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #else /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IPL_DEVICE (IPL_DEVICE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define INITRD_START (INITRD_START_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define INITRD_SIZE (INITRD_SIZE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OLDMEM_BASE (OLDMEM_BASE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OLDMEM_SIZE (OLDMEM_SIZE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define COMMAND_LINE (COMMAND_LINE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif /* _ASM_S390_SETUP_H */