^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_S390_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_S390_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci_hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm-generic/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/pci_clp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/pci_debug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/sclp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCIBIOS_MIN_IO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCIBIOS_MIN_MEM 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define pcibios_assign_all_busses() (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __iomem *pci_iomap(struct pci_dev *, int, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void pci_iounmap(struct pci_dev *, void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int pci_domain_nr(struct pci_bus *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int pci_proc_domain(struct pci_bus *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZPCI_BUS_NR 0 /* default bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZPCI_NR_DMA_SPACES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZPCI_NR_DEVICES CONFIG_PCI_NR_FUNCTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZPCI_DOMAIN_BITMAP_SIZE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if (ZPCI_NR_DEVICES > ZPCI_DOMAIN_BITMAP_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # error ZPCI_NR_DEVICES can not be bigger than ZPCI_DOMAIN_BITMAP_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif /* PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* PCI Function Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZPCI_FC_FN_ENABLED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZPCI_FC_ERROR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZPCI_FC_BLOCKED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ZPCI_FC_DMA_ENABLED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZPCI_FMB_DMA_COUNTER_VALID (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct zpci_fmb_fmt0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u64 dma_rbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u64 dma_wbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct zpci_fmb_fmt1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u64 rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u64 tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct zpci_fmb_fmt2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u64 consumed_work_units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u64 max_work_units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct zpci_fmb_fmt3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct zpci_fmb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 format : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 fmt_ind : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u64 last_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* common counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u64 ld_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u64 st_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u64 stb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u64 rpcit_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* format specific counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct zpci_fmb_fmt0 fmt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct zpci_fmb_fmt1 fmt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct zpci_fmb_fmt2 fmt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct zpci_fmb_fmt3 fmt3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } __packed __aligned(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum zpci_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ZPCI_FN_STATE_STANDBY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ZPCI_FN_STATE_CONFIGURED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ZPCI_FN_STATE_RESERVED = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ZPCI_FN_STATE_ONLINE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct zpci_bar_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct resource *res; /* bus resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *mio_wb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *mio_wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 val; /* bar start & 3 flag bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 map_idx; /* index into bar mapping array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 size; /* order 2 exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct s390_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ZPCI_FUNCTIONS_PER_BUS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct zpci_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct kref kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct zpci_dev *function[ZPCI_FUNCTIONS_PER_BUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct list_head resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct list_head bus_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct resource bus_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int pchid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int domain_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool multifunction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum pci_bus_speed max_bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Private data per function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct zpci_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct zpci_bus *zbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct list_head entry; /* list of all zpci_devices, needed for hotplug, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct list_head bus_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct kref kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct hotplug_slot hotplug_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum zpci_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 fid; /* function ID, used by sclp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 fh; /* function handle, used by insn's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u16 vfn; /* virtual function number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 pchid; /* physical channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 pfgid; /* function group ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 pft; /* pci function type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 rid_available : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 has_hp_slot : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 is_physfn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 util_str_avail : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 reserved : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int devfn; /* DEVFN part of the RID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 uid; /* user defined id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* IRQ stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u64 msi_addr; /* MSI address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int max_msi; /* maximum number of MSI's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int msi_first_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int msi_nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct airq_iv *aibv; /* adapter interrupt bit vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long aisb; /* number of the summary bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* DMA stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long *dma_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spinlock_t dma_table_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int tlb_refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spinlock_t iommu_bitmap_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long *iommu_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long *lazy_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long iommu_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long iommu_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int next_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct iommu_device iommu_dev; /* IOMMU core handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) char res_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool mio_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct zpci_bar_struct bars[PCI_STD_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u64 start_dma; /* Start of available DMA addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u64 end_dma; /* End of available DMA addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 dma_mask; /* DMA address space mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Function measurement block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct zpci_fmb *fmb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 fmb_update; /* update interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 fmb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* software counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) atomic64_t allocated_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) atomic64_t mapped_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) atomic64_t unmapped_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) enum pci_bus_speed max_bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct dentry *debugfs_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct s390_domain *s390_domain; /* s390 IOMMU domain data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline bool zdev_enabled(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return (zdev->fh & (1UL << 31)) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) extern const struct attribute_group *zpci_attr_groups[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern unsigned int s390_pci_force_floating __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern unsigned int s390_pci_no_rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) Prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ----------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Base stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int zpci_create_device(u32 fid, u32 fh, enum zpci_state state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void zpci_remove_device(struct zpci_dev *zdev, bool set_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int zpci_enable_device(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int zpci_disable_device(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void zpci_device_reserved(struct zpci_dev *zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bool zpci_is_device_configured(struct zpci_dev *zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int zpci_register_ioat(struct zpci_dev *, u8, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int zpci_unregister_ioat(struct zpci_dev *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void zpci_remove_reserved_devices(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* CLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int clp_setup_writeback_mio(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int clp_scan_pci_devices(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int clp_query_pci_fn(struct zpci_dev *zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int clp_enable_fh(struct zpci_dev *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int clp_disable_fh(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int clp_get_state(u32 fid, enum zpci_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* UID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void update_uid_checking(bool new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* IOMMU Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int zpci_init_iommu(struct zpci_dev *zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void zpci_destroy_iommu(struct zpci_dev *zdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline bool zpci_use_mio(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return static_branch_likely(&have_mio) && zdev->mio_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Error handling and recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void zpci_event_error(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void zpci_event_availability(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool zpci_is_enabled(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #else /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline void zpci_event_error(void *e) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline void zpci_event_availability(void *e) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #ifdef CONFIG_HOTPLUG_PCI_S390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int zpci_init_slot(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void zpci_exit_slot(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #else /* CONFIG_HOTPLUG_PCI_S390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline int zpci_init_slot(struct zpci_dev *zdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static inline void zpci_exit_slot(struct zpci_dev *zdev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif /* CONFIG_HOTPLUG_PCI_S390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline struct zpci_dev *to_zpci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct zpci_bus *zbus = pdev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return zbus->function[pdev->devfn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline struct zpci_dev *to_zpci_dev(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return to_zpci(to_pci_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct zpci_dev *get_zdev_by_fid(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int zpci_dma_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void zpci_dma_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int __init zpci_irq_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void __init zpci_irq_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* FMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int zpci_fmb_enable_device(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int zpci_fmb_disable_device(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int zpci_debug_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void zpci_debug_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void zpci_debug_init_device(struct zpci_dev *, const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void zpci_debug_exit_device(struct zpci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int zpci_report_error(struct pci_dev *, struct zpci_report_error_header *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Returns the node based on PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline int __pcibus_to_node(const struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return NUMA_NO_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static inline const struct cpumask *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) cpumask_of_pcibus(const struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return cpu_online_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif /* CONFIG_NUMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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