Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  S390 version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *    Copyright IBM Corp. 1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Derived from "include/asm-i386/io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _S390_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _S390_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/pci_io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define xlate_dev_mem_ptr xlate_dev_mem_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void *xlate_dev_mem_ptr(phys_addr_t phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Convert a virtual cached pointer to an uncached pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define xlate_dev_kmem_ptr(p)	p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IO_SPACE_LIMIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *ioremap_prot(phys_addr_t addr, size_t size, unsigned long prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *ioremap(phys_addr_t addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *ioremap_wc(phys_addr_t addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *ioremap_wt(phys_addr_t addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void iounmap(volatile void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void ioport_unmap(void __iomem *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  * s390 needs a private implementation of pci_iomap since ioremap with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  * offset parameter isn't sufficient. That's because BAR spaces are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * disjunctive on s390 so we need the bar parameter of pci_iomap to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  * the corresponding device and create the mapping cookie.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define pci_iomap pci_iomap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define pci_iomap_range pci_iomap_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define pci_iounmap pci_iounmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define pci_iomap_wc pci_iomap_wc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define pci_iomap_wc_range pci_iomap_wc_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ioremap ioremap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ioremap_wt ioremap_wt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ioremap_wc ioremap_wc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define memcpy_fromio(dst, src, count)	zpci_memcpy_fromio(dst, src, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define memcpy_toio(dst, src, count)	zpci_memcpy_toio(dst, src, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define memset_io(dst, val, count)	zpci_memset_io(dst, val, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define mmiowb()	zpci_barrier()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define __raw_readb	zpci_read_u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define __raw_readw	zpci_read_u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define __raw_readl	zpci_read_u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define __raw_readq	zpci_read_u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define __raw_writeb	zpci_write_u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define __raw_writew	zpci_write_u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define __raw_writel	zpci_write_u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define __raw_writeq	zpci_write_u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <asm-generic/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif