^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Common functionality for RV32 and RV64 BPF JIT compilers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Björn Töpel <bjorn.topel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _BPF_JIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _BPF_JIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bpf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/filter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static inline bool rvc_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) return IS_ENABLED(CONFIG_RISCV_ISA_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RV_REG_ZERO = 0, /* The constant value 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) RV_REG_RA = 1, /* Return address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) RV_REG_SP = 2, /* Stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) RV_REG_GP = 3, /* Global pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RV_REG_TP = 4, /* Thread pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RV_REG_T0 = 5, /* Temporaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RV_REG_T1 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RV_REG_T2 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RV_REG_FP = 8, /* Saved register/frame pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RV_REG_S1 = 9, /* Saved register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RV_REG_A0 = 10, /* Function argument/return values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RV_REG_A1 = 11, /* Function arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RV_REG_A2 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RV_REG_A3 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RV_REG_A4 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RV_REG_A5 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RV_REG_A6 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RV_REG_A7 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RV_REG_S2 = 18, /* Saved registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RV_REG_S3 = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RV_REG_S4 = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RV_REG_S5 = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RV_REG_S6 = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RV_REG_S7 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RV_REG_S8 = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RV_REG_S9 = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RV_REG_S10 = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RV_REG_S11 = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RV_REG_T3 = 28, /* Temporaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RV_REG_T4 = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RV_REG_T5 = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RV_REG_T6 = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline bool is_creg(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return (1 << reg) & (BIT(RV_REG_FP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) BIT(RV_REG_S1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) BIT(RV_REG_A0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) BIT(RV_REG_A1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) BIT(RV_REG_A2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) BIT(RV_REG_A3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BIT(RV_REG_A4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) BIT(RV_REG_A5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct rv_jit_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct bpf_prog *prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u16 *insns; /* RV insns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ninsns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int epilogue_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int *offset; /* BPF to RV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int stack_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Convert from ninsns to bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline int ninsns_rvoff(int ninsns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ninsns << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct rv_jit_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct bpf_binary_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 *image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct rv_jit_context ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void bpf_fill_ill_insns(void *area, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) memset(area, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void bpf_flush_icache(void *start, void *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) flush_icache_range((unsigned long)start, (unsigned long)end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Emit a 4-byte riscv instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void emit(const u32 insn, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ctx->insns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ctx->insns[ctx->ninsns] = insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ctx->insns[ctx->ninsns + 1] = (insn >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ctx->ninsns += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Emit a 2-byte riscv compressed instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void emitc(const u16 insn, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) BUILD_BUG_ON(!rvc_enabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ctx->insns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ctx->insns[ctx->ninsns] = insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ctx->ninsns++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline int epilogue_offset(struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int to = ctx->epilogue_offset, from = ctx->ninsns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ninsns_rvoff(to - from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Return -1 or inverted cond. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline int invert_bpf_cond(u8 cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (cond) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case BPF_JEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return BPF_JNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case BPF_JGT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return BPF_JLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case BPF_JLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return BPF_JGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case BPF_JGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return BPF_JLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case BPF_JLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return BPF_JGT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case BPF_JNE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return BPF_JEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case BPF_JSGT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return BPF_JSLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case BPF_JSLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return BPF_JSGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case BPF_JSGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return BPF_JSLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case BPF_JSLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return BPF_JSGT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline bool is_6b_int(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -(1L << 5) <= val && val < (1L << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline bool is_7b_uint(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return val < (1UL << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline bool is_8b_uint(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return val < (1UL << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline bool is_9b_uint(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return val < (1UL << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline bool is_10b_int(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -(1L << 9) <= val && val < (1L << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline bool is_10b_uint(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return val < (1UL << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline bool is_12b_int(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -(1L << 11) <= val && val < (1L << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline int is_12b_check(int off, int insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!is_12b_int(off)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_err("bpf-jit: insn=%d 12b < offset=%d not supported yet!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) insn, (int)off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline bool is_13b_int(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -(1L << 12) <= val && val < (1L << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline bool is_21b_int(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -(1L << 20) <= val && val < (1L << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int rv_offset(int insn, int off, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int from, to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) off++; /* BPF branch is from PC+1, RV is from PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) from = (insn > 0) ? ctx->offset[insn - 1] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) to = (insn + off > 0) ? ctx->offset[insn + off - 1] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ninsns_rvoff(to - from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Instruction formats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (rd << 7) | opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 imm11_5 = imm11_0 >> 5, imm4_0 = imm11_0 & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (imm4_0 << 7) | opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 imm4_1 = ((imm12_1 & 0xf) << 1) | ((imm12_1 & 0x400) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (imm4_1 << 7) | opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return (imm31_12 << 12) | (rd << 7) | opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ((imm20_1 & 0x400) >> 2) | ((imm20_1 & 0x7f800) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return (imm << 12) | (rd << 7) | opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 funct3, u8 rd, u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 funct7 = (funct5 << 2) | (aq << 1) | rl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* RISC-V compressed instruction formats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static inline u16 rv_cr_insn(u8 funct4, u8 rd, u8 rs2, u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return (funct4 << 12) | (rd << 7) | (rs2 << 2) | op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline u16 rv_ci_insn(u8 funct3, u32 imm6, u8 rd, u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return (funct3 << 13) | (rd << 7) | op | imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline u16 rv_css_insn(u8 funct3, u32 uimm, u8 rs2, u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return (funct3 << 13) | (uimm << 7) | (rs2 << 2) | op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline u16 rv_ciw_insn(u8 funct3, u32 uimm, u8 rd, u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return (funct3 << 13) | (uimm << 5) | ((rd & 0x7) << 2) | op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline u16 rv_cl_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (imm_lo << 5) | ((rd & 0x7) << 2) | op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline u16 rv_cs_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (imm_lo << 5) | ((rs2 & 0x7) << 2) | op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline u16 rv_ca_insn(u8 funct6, u8 rd, u8 funct2, u8 rs2, u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return (funct6 << 10) | ((rd & 0x7) << 7) | (funct2 << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ((rs2 & 0x7) << 2) | op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline u16 rv_cb_insn(u8 funct3, u32 imm6, u8 funct2, u8 rd, u8 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Instructions shared by both RV32 and RV64. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline u32 rv_addi(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return rv_i_insn(imm11_0, rs1, 0, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static inline u32 rv_andi(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return rv_i_insn(imm11_0, rs1, 7, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static inline u32 rv_ori(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return rv_i_insn(imm11_0, rs1, 6, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline u32 rv_xori(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return rv_i_insn(imm11_0, rs1, 4, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static inline u32 rv_slli(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return rv_i_insn(imm11_0, rs1, 1, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static inline u32 rv_srli(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return rv_i_insn(imm11_0, rs1, 5, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static inline u32 rv_srai(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static inline u32 rv_lui(u8 rd, u32 imm31_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return rv_u_insn(imm31_12, rd, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline u32 rv_auipc(u8 rd, u32 imm31_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return rv_u_insn(imm31_12, rd, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline u32 rv_add(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return rv_r_insn(0, rs2, rs1, 0, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline u32 rv_sub(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline u32 rv_sltu(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return rv_r_insn(0, rs2, rs1, 3, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline u32 rv_and(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return rv_r_insn(0, rs2, rs1, 7, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline u32 rv_or(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return rv_r_insn(0, rs2, rs1, 6, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline u32 rv_xor(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return rv_r_insn(0, rs2, rs1, 4, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline u32 rv_sll(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return rv_r_insn(0, rs2, rs1, 1, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static inline u32 rv_srl(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return rv_r_insn(0, rs2, rs1, 5, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static inline u32 rv_sra(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline u32 rv_mul(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return rv_r_insn(1, rs2, rs1, 0, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static inline u32 rv_jal(u8 rd, u32 imm20_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return rv_j_insn(imm20_1, rd, 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static inline u32 rv_jalr(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return rv_i_insn(imm11_0, rs1, 0, rd, 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static inline u32 rv_beq(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return rv_b_insn(imm12_1, rs2, rs1, 0, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline u32 rv_bne(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return rv_b_insn(imm12_1, rs2, rs1, 1, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline u32 rv_bltu(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return rv_b_insn(imm12_1, rs2, rs1, 6, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline u32 rv_bgtu(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return rv_bltu(rs2, rs1, imm12_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline u32 rv_bgeu(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return rv_b_insn(imm12_1, rs2, rs1, 7, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline u32 rv_bleu(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return rv_bgeu(rs2, rs1, imm12_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static inline u32 rv_blt(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return rv_b_insn(imm12_1, rs2, rs1, 4, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static inline u32 rv_bgt(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return rv_blt(rs2, rs1, imm12_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static inline u32 rv_bge(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return rv_b_insn(imm12_1, rs2, rs1, 5, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static inline u32 rv_ble(u8 rs1, u8 rs2, u16 imm12_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return rv_bge(rs2, rs1, imm12_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static inline u32 rv_lw(u8 rd, u16 imm11_0, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return rv_i_insn(imm11_0, rs1, 2, rd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static inline u32 rv_lbu(u8 rd, u16 imm11_0, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return rv_i_insn(imm11_0, rs1, 4, rd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline u32 rv_lhu(u8 rd, u16 imm11_0, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return rv_i_insn(imm11_0, rs1, 5, rd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline u32 rv_sb(u8 rs1, u16 imm11_0, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return rv_s_insn(imm11_0, rs2, rs1, 0, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline u32 rv_sh(u8 rs1, u16 imm11_0, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return rv_s_insn(imm11_0, rs2, rs1, 1, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static inline u32 rv_sw(u8 rs1, u16 imm11_0, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return rv_s_insn(imm11_0, rs2, rs1, 2, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline u32 rv_amoadd_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return rv_amo_insn(0, aq, rl, rs2, rs1, 2, rd, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* RVC instrutions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static inline u16 rvc_addi4spn(u8 rd, u32 imm10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) imm = ((imm10 & 0x30) << 2) | ((imm10 & 0x3c0) >> 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ((imm10 & 0x4) >> 1) | ((imm10 & 0x8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return rv_ciw_insn(0x0, imm, rd, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static inline u16 rvc_lw(u8 rd, u32 imm7, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 imm_hi, imm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) imm_hi = (imm7 & 0x38) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return rv_cl_insn(0x2, imm_hi, rs1, imm_lo, rd, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static inline u16 rvc_sw(u8 rs1, u32 imm7, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 imm_hi, imm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) imm_hi = (imm7 & 0x38) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return rv_cs_insn(0x6, imm_hi, rs1, imm_lo, rs2, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static inline u16 rvc_addi(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return rv_ci_insn(0, imm6, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static inline u16 rvc_li(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return rv_ci_insn(0x2, imm6, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static inline u16 rvc_addi16sp(u32 imm10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) imm = ((imm10 & 0x200) >> 4) | (imm10 & 0x10) | ((imm10 & 0x40) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ((imm10 & 0x180) >> 6) | ((imm10 & 0x20) >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return rv_ci_insn(0x3, imm, RV_REG_SP, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static inline u16 rvc_lui(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return rv_ci_insn(0x3, imm6, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static inline u16 rvc_srli(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return rv_cb_insn(0x4, imm6, 0, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static inline u16 rvc_srai(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return rv_cb_insn(0x4, imm6, 0x1, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static inline u16 rvc_andi(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return rv_cb_insn(0x4, imm6, 0x2, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static inline u16 rvc_sub(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return rv_ca_insn(0x23, rd, 0, rs, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static inline u16 rvc_xor(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return rv_ca_insn(0x23, rd, 0x1, rs, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static inline u16 rvc_or(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return rv_ca_insn(0x23, rd, 0x2, rs, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static inline u16 rvc_and(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return rv_ca_insn(0x23, rd, 0x3, rs, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static inline u16 rvc_slli(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return rv_ci_insn(0, imm6, rd, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static inline u16 rvc_lwsp(u8 rd, u32 imm8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) imm = ((imm8 & 0xc0) >> 6) | (imm8 & 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return rv_ci_insn(0x2, imm, rd, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static inline u16 rvc_jr(u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return rv_cr_insn(0x8, rs1, RV_REG_ZERO, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static inline u16 rvc_mv(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return rv_cr_insn(0x8, rd, rs, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static inline u16 rvc_jalr(u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return rv_cr_insn(0x9, rs1, RV_REG_ZERO, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static inline u16 rvc_add(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return rv_cr_insn(0x9, rd, rs, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static inline u16 rvc_swsp(u32 imm8, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) imm = (imm8 & 0x3c) | ((imm8 & 0xc0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return rv_css_insn(0x6, imm, rs2, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * RV64-only instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * These instructions are not available on RV32. Wrap them below a #if to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * ensure that the RV32 JIT doesn't emit any of these instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #if __riscv_xlen == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static inline u32 rv_addiw(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return rv_i_insn(imm11_0, rs1, 0, rd, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static inline u32 rv_slliw(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return rv_i_insn(imm11_0, rs1, 1, rd, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static inline u32 rv_srliw(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return rv_i_insn(imm11_0, rs1, 5, rd, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static inline u32 rv_sraiw(u8 rd, u8 rs1, u16 imm11_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static inline u32 rv_addw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return rv_r_insn(0, rs2, rs1, 0, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static inline u32 rv_subw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static inline u32 rv_sllw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return rv_r_insn(0, rs2, rs1, 1, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static inline u32 rv_srlw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return rv_r_insn(0, rs2, rs1, 5, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static inline u32 rv_sraw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static inline u32 rv_ld(u8 rd, u16 imm11_0, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return rv_i_insn(imm11_0, rs1, 3, rd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static inline u32 rv_lwu(u8 rd, u16 imm11_0, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return rv_i_insn(imm11_0, rs1, 6, rd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static inline u32 rv_sd(u8 rs1, u16 imm11_0, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return rv_s_insn(imm11_0, rs2, rs1, 3, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static inline u32 rv_amoadd_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return rv_amo_insn(0, aq, rl, rs2, rs1, 3, rd, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* RV64-only RVC instructions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static inline u16 rvc_ld(u8 rd, u32 imm8, u8 rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 imm_hi, imm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) imm_hi = (imm8 & 0x38) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) imm_lo = (imm8 & 0xc0) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return rv_cl_insn(0x3, imm_hi, rs1, imm_lo, rd, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static inline u16 rvc_sd(u8 rs1, u32 imm8, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u32 imm_hi, imm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) imm_hi = (imm8 & 0x38) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) imm_lo = (imm8 & 0xc0) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return rv_cs_insn(0x7, imm_hi, rs1, imm_lo, rs2, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static inline u16 rvc_subw(u8 rd, u8 rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return rv_ca_insn(0x27, rd, 0, rs, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static inline u16 rvc_addiw(u8 rd, u32 imm6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return rv_ci_insn(0x1, imm6, rd, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static inline u16 rvc_ldsp(u8 rd, u32 imm9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) imm = ((imm9 & 0x1c0) >> 6) | (imm9 & 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return rv_ci_insn(0x3, imm, rd, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) imm = (imm9 & 0x38) | ((imm9 & 0x1c0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return rv_css_insn(0x7, imm, rs2, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #endif /* __riscv_xlen == 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Helper functions that emit RVC instructions when possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static inline void emit_jalr(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (rvc_enabled() && rd == RV_REG_RA && rs && !imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) emitc(rvc_jalr(rs), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else if (rvc_enabled() && !rd && rs && !imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) emitc(rvc_jr(rs), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) emit(rv_jalr(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static inline void emit_mv(u8 rd, u8 rs, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (rvc_enabled() && rd && rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) emitc(rvc_mv(rd, rs), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) emit(rv_addi(rd, rs, 0), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static inline void emit_add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (rvc_enabled() && rd && rd == rs1 && rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) emitc(rvc_add(rd, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) emit(rv_add(rd, rs1, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static inline void emit_addi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) emitc(rvc_addi16sp(imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) else if (rvc_enabled() && is_creg(rd) && rs == RV_REG_SP && is_10b_uint(imm) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) !(imm & 0x3) && imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) emitc(rvc_addi4spn(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) else if (rvc_enabled() && rd && rd == rs && imm && is_6b_int(imm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) emitc(rvc_addi(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) emit(rv_addi(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static inline void emit_li(u8 rd, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (rvc_enabled() && rd && is_6b_int(imm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) emitc(rvc_li(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) emit(rv_addi(rd, RV_REG_ZERO, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static inline void emit_lui(u8 rd, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) emitc(rvc_lui(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) emit(rv_lui(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static inline void emit_slli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (rvc_enabled() && rd && rd == rs && imm && (u32)imm < __riscv_xlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) emitc(rvc_slli(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) emit(rv_slli(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static inline void emit_andi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (rvc_enabled() && is_creg(rd) && rd == rs && is_6b_int(imm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) emitc(rvc_andi(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) emit(rv_andi(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static inline void emit_srli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) emitc(rvc_srli(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) emit(rv_srli(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static inline void emit_srai(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) emitc(rvc_srai(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) emit(rv_srai(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static inline void emit_sub(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) emitc(rvc_sub(rd, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) emit(rv_sub(rd, rs1, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static inline void emit_or(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) emitc(rvc_or(rd, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) emit(rv_or(rd, rs1, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static inline void emit_and(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) emitc(rvc_and(rd, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) emit(rv_and(rd, rs1, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static inline void emit_xor(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) emitc(rvc_xor(rd, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) emit(rv_xor(rd, rs1, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static inline void emit_lw(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_8b_uint(off) && !(off & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) emitc(rvc_lwsp(rd, off), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_7b_uint(off) && !(off & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) emitc(rvc_lw(rd, off, rs1), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) emit(rv_lw(rd, off, rs1), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static inline void emit_sw(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (rvc_enabled() && rs1 == RV_REG_SP && is_8b_uint(off) && !(off & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) emitc(rvc_swsp(off, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_7b_uint(off) && !(off & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) emitc(rvc_sw(rs1, off, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) emit(rv_sw(rs1, off, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* RV64-only helper functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #if __riscv_xlen == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static inline void emit_addiw(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (rvc_enabled() && rd && rd == rs && is_6b_int(imm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) emitc(rvc_addiw(rd, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) emit(rv_addiw(rd, rs, imm), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static inline void emit_ld(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_9b_uint(off) && !(off & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) emitc(rvc_ldsp(rd, off), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_8b_uint(off) && !(off & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) emitc(rvc_ld(rd, off, rs1), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) emit(rv_ld(rd, off, rs1), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static inline void emit_sd(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (rvc_enabled() && rs1 == RV_REG_SP && is_9b_uint(off) && !(off & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) emitc(rvc_sdsp(off, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_8b_uint(off) && !(off & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) emitc(rvc_sd(rs1, off, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) emit(rv_sd(rs1, off, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) emitc(rvc_subw(rd, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) emit(rv_subw(rd, rs1, rs2), ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif /* __riscv_xlen == 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) void bpf_jit_build_prologue(struct rv_jit_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) void bpf_jit_build_epilogue(struct rv_jit_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) bool extra_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #endif /* _BPF_JIT_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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