Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2012 Regents of the University of California
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2014 Darius Rad <darius@bluespec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017 SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm-generic/mman-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static long riscv_sys_mmap(unsigned long addr, unsigned long len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 			   unsigned long prot, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			   unsigned long fd, off_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 			   unsigned long page_shift_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	if ((prot & PROT_WRITE) && (prot & PROT_EXEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		if (unlikely(!(prot & PROT_READ)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	return ksys_mmap_pgoff(addr, len, prot, flags, fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			       offset >> (PAGE_SHIFT - page_shift_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	unsigned long, prot, unsigned long, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned long, fd, off_t, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned long, prot, unsigned long, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned long, fd, off_t, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	 * Note that the shift for mmap2 is constant (12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	 * regardless of PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  * having a direct 'fence.i' instruction available to userspace (which we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  * can't trap!), that's not actually viable when running on Linux because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  * kernel might schedule a process on another hart.  There is no way for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * userspace to handle this without invoking the kernel (as it doesn't know the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * thread->hart mappings), so we've defined a RISC-V specific system call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * flush the instruction cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  * sys_riscv_flush_icache() is defined to flush the instruction cache over an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  * address range, with the flush applying to either all threads or just the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  * caller.  We don't currently do anything with the address range, that's just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  * in there for forwards compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	uintptr_t, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	/* Check the reserved flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }