Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012 Regents of the University of California
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/csr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/image.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "efi-header.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) ENTRY(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	 * Image header expected by Linux boot-loaders. The image header data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	 * structure is described in asm/image.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	 * Do not modify it without modifying the structure and all bootloaders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	 * that expects this header format!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #ifdef CONFIG_EFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	 * This instruction decodes to "MZ" ASCII required by UEFI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	c.li s4,-13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	j _start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	/* jump to start kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	j _start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.balign 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #ifdef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/* Image load offset (0MB) from start of RAM for M-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.dword 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #if __riscv_xlen == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* Image load offset(2MB) from start of RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.dword 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* Image load offset(4MB) from start of RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.dword 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* Effective size of kernel image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.dword _end - _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.dword __HEAD_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.word RISCV_HEADER_VERSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.dword 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.ascii RISCV_IMAGE_MAGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.ascii RISCV_IMAGE_MAGIC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #ifdef CONFIG_EFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.word pe_head_start - _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) pe_head_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	__EFI_PE_HEADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) relocate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* Relocate return address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	li a1, PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	la a2, _start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	sub a1, a1, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	add ra, ra, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* Point stvec to virtual address of intruction after satp write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	la a2, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	add a2, a2, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	csrw CSR_TVEC, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Compute satp for kernel page tables, but don't load it yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	srl a2, a0, PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	li a1, SATP_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	or a2, a2, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * Load trampoline page directory, which will cause us to trap to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * stvec if VA != PA, or simply fall through if VA == PA.  We need a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * full fence here because setup_vm() just wrote these PTEs and we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * to ensure the new translations are in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	la a0, trampoline_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	srl a0, a0, PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	or a0, a0, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	sfence.vma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	csrw CSR_SATP, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Set trap vector to spin forever to help debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	la a0, .Lsecondary_park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	csrw CSR_TVEC, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Reload the global pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .option push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .option norelax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	la gp, __global_pointer$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .option pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * Switch to kernel page tables.  A full fence is necessary in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * avoid using the trampoline translations, which are only correct for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * the first superpage.  Fetching the fence is guarnteed to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * because that first superpage is translated the same way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	csrw CSR_SATP, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	sfence.vma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.global secondary_start_sbi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) secondary_start_sbi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	csrw CSR_IE, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	csrw CSR_IP, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Load the global pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.option push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.option norelax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		la gp, __global_pointer$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.option pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * Disable FPU to detect illegal usage of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * floating point in kernel space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	li t0, SR_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	csrc CSR_STATUS, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Set trap vector to spin forever to help debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	la a3, .Lsecondary_park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	csrw CSR_TVEC, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	slli a3, a0, LGREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	la a4, __cpu_up_stack_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	la a5, __cpu_up_task_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	add a4, a3, a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	add a5, a3, a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	REG_L sp, (a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	REG_L tp, (a5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.global secondary_start_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) secondary_start_common:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* Enable virtual memory and relocate to virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	la a0, swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	call relocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	call setup_trap_vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	tail smp_callin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) setup_trap_vector:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* Set trap vector to exception handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	la a0, handle_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	csrw CSR_TVEC, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * Set sup0 scratch register to 0, indicating to exception vector that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 * we are presently executing in kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	csrw CSR_SCRATCH, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .Lsecondary_park:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* We lack SMP support or have too many harts, so park this hart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	j .Lsecondary_park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) END(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ENTRY(_start_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	csrw CSR_IE, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	csrw CSR_IP, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* flush the instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	fence.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* Reset all registers except ra, a0, a1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	call reset_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * Setup a PMP to permit access to all of memory.  Some machines may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * not implement PMPs, so we set up a quick trap handler to just skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * touching the PMPs on any trap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	la a0, pmp_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	csrw CSR_TVEC, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	li a0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	csrw CSR_PMPADDR0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	csrw CSR_PMPCFG0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pmp_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * The hartid in a0 is expected later on, and we have no firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * to hand it to us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	csrr a0, CSR_MHARTID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif /* CONFIG_RISCV_M_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Load the global pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .option push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .option norelax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	la gp, __global_pointer$
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .option pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * Disable FPU to detect illegal usage of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * floating point in kernel space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	li t0, SR_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	csrc CSR_STATUS, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	li t0, CONFIG_NR_CPUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	blt a0, t0, .Lgood_cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	tail .Lsecondary_park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .Lgood_cores:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* Pick one hart to run the main boot sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	la a3, hart_lottery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	li a2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	amoadd.w a3, a2, (a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	bnez a3, .Lsecondary_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* Clear BSS for flat non-ELF images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	la a3, __bss_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	la a4, __bss_stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ble a4, a3, clear_bss_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) clear_bss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	REG_S zero, (a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	add a3, a3, RISCV_SZPTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	blt a3, a4, clear_bss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clear_bss_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Save hart ID and DTB physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	mv s0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mv s1, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	la a2, boot_cpu_hartid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	REG_S a0, (a2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* Initialize page tables and relocate to virtual addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	la sp, init_thread_union + THREAD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mv a0, s1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	call setup_vm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	la a0, early_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	call relocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	call setup_trap_vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* Restore C environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	la tp, init_task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	sw zero, TASK_TI_CPU(tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	la sp, init_thread_union + THREAD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #ifdef CONFIG_KASAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	call kasan_early_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* Start the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	call soc_early_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	tail start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .Lsecondary_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Set trap vector to spin forever to help debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	la a3, .Lsecondary_park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	csrw CSR_TVEC, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	slli a3, a0, LGREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	la a1, __cpu_up_stack_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	la a2, __cpu_up_task_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	add a1, a3, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	add a2, a3, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 * This hart didn't win the lottery, so we wait for the winning hart to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 * get far enough along the boot process that it should continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .Lwait_for_cpu_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* FIXME: We should WFI to save some energy here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	REG_L sp, (a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	REG_L tp, (a2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	beqz sp, .Lwait_for_cpu_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	beqz tp, .Lwait_for_cpu_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	fence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	tail secondary_start_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) END(_start_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifdef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ENTRY(reset_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	li	sp, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	li	gp, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	li	tp, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	li	t0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	li	t1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	li	t2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	li	s0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	li	s1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	li	a2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	li	a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	li	a4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	li	a5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	li	a6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	li	a7, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	li	s2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	li	s3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	li	s4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	li	s5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	li	s6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	li	s7, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	li	s8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	li	s9, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	li	s10, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	li	s11, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	li	t3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	li	t4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	li	t5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	li	t6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	csrw	CSR_SCRATCH, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #ifdef CONFIG_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	csrr	t0, CSR_MISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	beqz	t0, .Lreset_regs_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	li	t1, SR_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	csrs	CSR_STATUS, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	fmv.s.x	f0, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	fmv.s.x	f1, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	fmv.s.x	f2, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	fmv.s.x	f3, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	fmv.s.x	f4, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	fmv.s.x	f5, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	fmv.s.x	f6, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	fmv.s.x	f7, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	fmv.s.x	f8, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	fmv.s.x	f9, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	fmv.s.x	f10, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	fmv.s.x	f11, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	fmv.s.x	f12, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	fmv.s.x	f13, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	fmv.s.x	f14, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	fmv.s.x	f15, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	fmv.s.x	f16, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	fmv.s.x	f17, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	fmv.s.x	f18, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	fmv.s.x	f19, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	fmv.s.x	f20, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	fmv.s.x	f21, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	fmv.s.x	f22, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	fmv.s.x	f23, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	fmv.s.x	f24, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	fmv.s.x	f25, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	fmv.s.x	f26, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	fmv.s.x	f27, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	fmv.s.x	f28, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	fmv.s.x	f29, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	fmv.s.x	f30, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	fmv.s.x	f31, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	csrw	fcsr, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* note that the caller must clear SR_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif /* CONFIG_FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .Lreset_regs_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) END(reset_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif /* CONFIG_RISCV_M_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __PAGE_ALIGNED_BSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	/* Empty zero page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.balign PAGE_SIZE