Orange Pi5 kernel

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copied from arch/arm64/kernel/cpufeature.c
 *
 * Copyright (C) 2015 ARM Ltd.
 * Copyright (C) 2017 SiFive
 */
 
#include <linux/bitmap.h>
#include <linux/of.h>
#include <asm/processor.h>
#include <asm/hwcap.h>
#include <asm/smp.h>
#include <asm/switch_to.h>
 
unsigned long elf_hwcap __read_mostly;
 
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 
#ifdef CONFIG_FPU
bool has_fpu __read_mostly;
#endif
 
/**
 * riscv_isa_extension_base() - Get base extension word
 *
 * @isa_bitmap: ISA bitmap to use
 * Return: base extension word as unsigned long value
 *
 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
 */
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
{
<------>if (!isa_bitmap)
<------><------>return riscv_isa[0];
<------>return isa_bitmap[0];
}
EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
 
/**
 * __riscv_isa_extension_available() - Check whether given extension
 * is available or not
 *
 * @isa_bitmap: ISA bitmap to use
 * @bit: bit position of the desired extension
 * Return: true or false
 *
 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
 */
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
{
<------>const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
 
<------>if (bit >= RISCV_ISA_EXT_MAX)
<------><------>return false;
 
<------>return test_bit(bit, bmap) ? true : false;
}
EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
 
void riscv_fill_hwcap(void)
{
<------>struct device_node *node;
<------>const char *isa;
<------>char print_str[BITS_PER_LONG + 1];
<------>size_t i, j, isa_len;
<------>static unsigned long isa2hwcap[256] = {0};
 
<------>isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
<------>isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
<------>isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
<------>isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
<------>isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
<------>isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
 
<------>elf_hwcap = 0;
 
<------>bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 
<------>for_each_of_cpu_node(node) {
<------><------>unsigned long this_hwcap = 0;
<------><------>unsigned long this_isa = 0;
 
<------><------>if (riscv_of_processor_hartid(node) < 0)
<------><------><------>continue;
 
<------><------>if (of_property_read_string(node, "riscv,isa", &isa)) {
<------><------><------>pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
<------><------><------>continue;
<------><------>}
 
<------><------>i = 0;
<------><------>isa_len = strlen(isa);
#if IS_ENABLED(CONFIG_32BIT)
<------><------>if (!strncmp(isa, "rv32", 4))
<------><------><------>i += 4;
#elif IS_ENABLED(CONFIG_64BIT)
<------><------>if (!strncmp(isa, "rv64", 4))
<------><------><------>i += 4;
#endif
<------><------>for (; i < isa_len; ++i) {
<------><------><------>this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
<------><------><------>/*
<------><------><------> * TODO: X, Y and Z extension parsing for Host ISA
<------><------><------> * bitmap will be added in-future.
<------><------><------> */
<------><------><------>if ('a' <= isa[i] && isa[i] < 'x')
<------><------><------><------>this_isa |= (1UL << (isa[i] - 'a'));
<------><------>}
 
<------><------>/*
<------><------> * All "okay" hart should have same isa. Set HWCAP based on
<------><------> * common capabilities of every "okay" hart, in case they don't
<------><------> * have.
<------><------> */
<------><------>if (elf_hwcap)
<------><------><------>elf_hwcap &= this_hwcap;
<------><------>else
<------><------><------>elf_hwcap = this_hwcap;
 
<------><------>if (riscv_isa[0])
<------><------><------>riscv_isa[0] &= this_isa;
<------><------>else
<------><------><------>riscv_isa[0] = this_isa;
<------>}
 
<------>/* We don't support systems with F but without D, so mask those out
<------> * here. */
<------>if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
<------><------>pr_info("This kernel does not support systems with F but not D\n");
<------><------>elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
<------>}
 
<------>memset(print_str, 0, sizeof(print_str));
<------>for (i = 0, j = 0; i < BITS_PER_LONG; i++)
<------><------>if (riscv_isa[0] & BIT_MASK(i))
<------><------><------>print_str[j++] = (char)('a' + i);
<------>pr_info("riscv: ISA extensions %s\n", print_str);
 
<------>memset(print_str, 0, sizeof(print_str));
<------>for (i = 0, j = 0; i < BITS_PER_LONG; i++)
<------><------>if (elf_hwcap & BIT_MASK(i))
<------><------><------>print_str[j++] = (char)('a' + i);
<------>pr_info("riscv: ELF capabilities %s\n", print_str);
 
#ifdef CONFIG_FPU
<------>if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
<------><------>has_fpu = true;
#endif
}