^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * which was based on arch/arm/include/io.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996-2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2014 Regents of the University of California
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _ASM_RISCV_MMIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _ASM_RISCV_MMIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mmiowb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Generic IO read/write. These perform native-endian accesses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __raw_writeb __raw_writeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __raw_writew __raw_writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline void __raw_writew(u16 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define __raw_writel __raw_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline void __raw_writel(u32 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define __raw_writeq __raw_writeq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __raw_readb __raw_readb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline u8 __raw_readb(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define __raw_readw __raw_readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline u16 __raw_readw(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define __raw_readl __raw_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline u32 __raw_readl(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define __raw_readq __raw_readq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline u64 __raw_readq(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Unordered I/O memory access primitives. These are even more relaxed than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * the relaxed versions, as they don't even order accesses between successive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * operations to the I/O regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Relaxed I/O memory access primitives. These follow the Device memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * ordering rules but do not guarantee any ordering relative to Normal memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * accesses. These are defined to order the indicated access (either a read or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * write) with all other I/O memory accesses. Since the platform specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * defines that all I/O regions are strongly ordered on channel 2, no explicit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * fences are required to enforce this ordering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* FIXME: These are now the same as asm-generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define __io_rbr() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define __io_rar() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define __io_rbw() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define __io_raw() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * I/O memory access primitives. Reads are ordered relative to any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * following Normal memory access. Writes are ordered relative to any prior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Normal memory access. The memory barriers here are necessary as RISC-V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * doesn't define any ordering between the memory space and the I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define __io_br() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define __io_aw() mmiowb_set_pending()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif /* _ASM_RISCV_MMIO_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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