Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #ifndef _ASM_RISCV_IMAGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define _ASM_RISCV_IMAGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define RISCV_IMAGE_MAGIC	"RISCV\0\0\0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define RISCV_IMAGE_MAGIC2	"RSC\x05"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define RISCV_IMAGE_FLAG_BE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RISCV_IMAGE_FLAG_BE_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RISCV_IMAGE_FLAG_LE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RISCV_IMAGE_FLAG_BE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #error conversion of header fields to LE not yet implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __HEAD_FLAG_BE		RISCV_IMAGE_FLAG_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define __HEAD_FLAG(field)	(__HEAD_FLAG_##field << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				RISCV_IMAGE_FLAG_##field##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __HEAD_FLAGS		(__HEAD_FLAG(BE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RISCV_HEADER_VERSION_MAJOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RISCV_HEADER_VERSION_MINOR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			      RISCV_HEADER_VERSION_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * struct riscv_image_header - riscv kernel image header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * @code0:		Executable code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * @code1:		Executable code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * @text_offset:	Image load offset (little endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * @image_size:		Effective Image size (little endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * @flags:		kernel flags (little endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * @version:		version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * @res1:		reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * @res2:		reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * @magic:		Magic number (RISC-V specific; deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * @magic2:		Magic number 2 (to match the ARM64 'magic' field pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * @res3:		reserved (will be used for PE COFF offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  * The intention is for this header format to be shared between multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  * architectures to avoid a proliferation of image header formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct riscv_image_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	u32 code0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	u32 code1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	u64 text_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u64 image_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	u32 res1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u64 res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	u64 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	u32 magic2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	u32 res3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* _ASM_RISCV_IMAGE_H */