Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copied from arch/arm64/include/asm/hwcap.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2017 SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ASM_RISCV_HWCAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ASM_RISCV_HWCAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <uapi/asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * This yields a mask that user programs can use to figure out what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * instruction set this cpu supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ELF_HWCAP		(elf_hwcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	CAP_HWCAP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern unsigned long elf_hwcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RISCV_ISA_EXT_a		('a' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RISCV_ISA_EXT_c		('c' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RISCV_ISA_EXT_d		('d' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RISCV_ISA_EXT_f		('f' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RISCV_ISA_EXT_h		('h' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RISCV_ISA_EXT_i		('i' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RISCV_ISA_EXT_m		('m' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RISCV_ISA_EXT_s		('s' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RISCV_ISA_EXT_u		('u' - 'a')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RISCV_ISA_EXT_MAX	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define riscv_isa_extension_available(isa_bitmap, ext)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif /* _ASM_RISCV_HWCAP_H */