^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef _ASM_RISCV_FENCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define _ASM_RISCV_FENCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define RISCV_RELEASE_BARRIER "\tfence rw, w\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define RISCV_ACQUIRE_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RISCV_RELEASE_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #endif /* _ASM_RISCV_FENCE_H */