Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Regents of the University of California
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _ASM_RISCV_CSR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _ASM_RISCV_CSR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* Status register flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SR_FS_OFF	_AC(0x00000000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SR_FS_INITIAL	_AC(0x00002000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SR_FS_CLEAN	_AC(0x00004000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SR_FS_DIRTY	_AC(0x00006000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SR_XS_OFF	_AC(0x00000000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SR_XS_INITIAL	_AC(0x00008000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SR_XS_CLEAN	_AC(0x00010000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SR_XS_DIRTY	_AC(0x00018000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #ifndef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* SATP flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #ifndef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SATP_PPN	_AC(0x003FFFFF, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SATP_MODE_32	_AC(0x80000000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SATP_MODE	SATP_MODE_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SATP_MODE_39	_AC(0x8000000000000000, UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SATP_MODE	SATP_MODE_39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Exception cause high bit - is an interrupt if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Interrupt causes (minus the high bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IRQ_S_SOFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IRQ_M_SOFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IRQ_S_TIMER		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IRQ_M_TIMER		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IRQ_S_EXT		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IRQ_M_EXT		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Exception causes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define EXC_INST_MISALIGNED	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define EXC_INST_ACCESS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define EXC_BREAKPOINT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define EXC_LOAD_ACCESS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define EXC_STORE_ACCESS	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define EXC_SYSCALL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define EXC_INST_PAGE_FAULT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define EXC_LOAD_PAGE_FAULT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define EXC_STORE_PAGE_FAULT	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* PMP configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PMP_R			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PMP_W			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PMP_X			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PMP_A			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PMP_A_TOR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PMP_A_NA4		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PMP_A_NAPOT		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PMP_L			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* symbolic CSR names: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CSR_CYCLE		0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CSR_TIME		0xc01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CSR_INSTRET		0xc02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CSR_CYCLEH		0xc80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CSR_TIMEH		0xc81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CSR_INSTRETH		0xc82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CSR_SSTATUS		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CSR_SIE			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CSR_STVEC		0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CSR_SCOUNTEREN		0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CSR_SSCRATCH		0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CSR_SEPC		0x141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CSR_SCAUSE		0x142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CSR_STVAL		0x143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CSR_SIP			0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CSR_SATP		0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CSR_MSTATUS		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CSR_MISA		0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CSR_MIE			0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CSR_MTVEC		0x305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CSR_MSCRATCH		0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CSR_MEPC		0x341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CSR_MCAUSE		0x342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CSR_MTVAL		0x343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CSR_MIP			0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CSR_PMPCFG0		0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CSR_PMPADDR0		0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CSR_MHARTID		0xf14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_RISCV_M_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define CSR_STATUS	CSR_MSTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define CSR_IE		CSR_MIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define CSR_TVEC	CSR_MTVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define CSR_SCRATCH	CSR_MSCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define CSR_EPC	CSR_MEPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define CSR_CAUSE	CSR_MCAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define CSR_TVAL	CSR_MTVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define CSR_IP		CSR_MIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define SR_IE		SR_MIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define SR_PIE		SR_MPIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define SR_PP		SR_MPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define RV_IRQ_SOFT		IRQ_M_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) # define RV_IRQ_TIMER	IRQ_M_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define RV_IRQ_EXT		IRQ_M_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else /* CONFIG_RISCV_M_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define CSR_STATUS	CSR_SSTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define CSR_IE		CSR_SIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define CSR_TVEC	CSR_STVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define CSR_SCRATCH	CSR_SSCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define CSR_EPC	CSR_SEPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define CSR_CAUSE	CSR_SCAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define CSR_TVAL	CSR_STVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define CSR_IP		CSR_SIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define SR_IE		SR_SIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define SR_PIE		SR_SPIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define SR_PP		SR_SPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define RV_IRQ_SOFT		IRQ_S_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define RV_IRQ_TIMER	IRQ_S_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define RV_IRQ_EXT		IRQ_S_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif /* CONFIG_RISCV_M_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define csr_swap(csr, val)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned long __v = (unsigned long)(val);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			      : "=r" (__v) : "rK" (__v)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	__v;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define csr_read(csr)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	register unsigned long __v;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			      : "=r" (__v) :			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	__v;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define csr_write(csr, val)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned long __v = (unsigned long)(val);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			      : : "rK" (__v)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define csr_read_set(csr, val)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned long __v = (unsigned long)(val);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			      : "=r" (__v) : "rK" (__v)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	__v;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define csr_set(csr, val)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	unsigned long __v = (unsigned long)(val);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			      : : "rK" (__v)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define csr_read_clear(csr, val)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	unsigned long __v = (unsigned long)(val);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			      : "=r" (__v) : "rK" (__v)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	__v;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define csr_clear(csr, val)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned long __v = (unsigned long)(val);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			      : : "rK" (__v)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			      : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif /* _ASM_RISCV_CSR_H */