Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2015 Regents of the University of California
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _ASM_RISCV_ASM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _ASM_RISCV_ASM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_STR(x)	x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __ASM_STR(x)	#x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #if __riscv_xlen == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __REG_SEL(a, b)	__ASM_STR(a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #elif __riscv_xlen == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __REG_SEL(a, b)	__ASM_STR(b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #error "Unexpected __riscv_xlen"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_L		__REG_SEL(ld, lw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_S		__REG_SEL(sd, sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_SC		__REG_SEL(sc.d, sc.w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SZREG		__REG_SEL(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LGREG		__REG_SEL(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if __SIZEOF_POINTER__ == 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RISCV_PTR		.dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RISCV_SZPTR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RISCV_LGPTR		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RISCV_PTR		".dword"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RISCV_SZPTR		"8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RISCV_LGPTR		"3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #elif __SIZEOF_POINTER__ == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RISCV_PTR		.word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RISCV_SZPTR		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RISCV_LGPTR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RISCV_PTR		".word"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RISCV_SZPTR		"4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RISCV_LGPTR		"2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #error "Unexpected __SIZEOF_POINTER__"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #if (__SIZEOF_INT__ == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RISCV_INT		__ASM_STR(.word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RISCV_SZINT		__ASM_STR(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RISCV_LGINT		__ASM_STR(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #error "Unexpected __SIZEOF_INT__"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if (__SIZEOF_SHORT__ == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RISCV_SHORT		__ASM_STR(.half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RISCV_SZSHORT		__ASM_STR(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RISCV_LGSHORT		__ASM_STR(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #error "Unexpected __SIZEOF_SHORT__"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* _ASM_RISCV_ASM_H */