^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* ppc.h -- Header file for PowerPC opcode table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Copyright (C) 1994-2016 Free Software Foundation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Written by Ian Lance Taylor, Cygnus Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) This file is part of GDB, GAS, and the GNU binutils.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) GDB, GAS, and the GNU binutils are free software; you can redistribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) them and/or modify them under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) License as published by the Free Software Foundation; either version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 1, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) GDB, GAS, and the GNU binutils are distributed in the hope that they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) will be useful, but WITHOUT ANY WARRANTY; without even the implied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) the GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) along with this file; see the file COPYING. If not, write to the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef PPC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PPC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef __cplusplus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) typedef uint64_t ppc_cpu_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* The opcode table is an array of struct powerpc_opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct powerpc_opcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* The opcode name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* The opcode itself. Those bits which will be filled in with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) operands are zeroes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* The opcode mask. This is used by the disassembler. This is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mask containing ones indicating those bits which must match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) opcode field, and zeroes indicating those bits which need not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) match (and are presumably filled in by operands). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* One bit flags for the opcode. These are used to indicate which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) specific processors support the instructions. The defined values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) are listed below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ppc_cpu_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* One bit flags for the opcode. These are used to indicate which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) specific processors no longer support the instructions. The defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) values are listed below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ppc_cpu_t deprecated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* An array of operand codes. Each code is an index into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) operand table. They appear in the order which the operands must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) appear in assembly code, and are terminated by a zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned char operands[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* The table itself is sorted by major opcode number, and is otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) in the order in which the disassembler should consider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) instructions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern const struct powerpc_opcode powerpc_opcodes[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern const int powerpc_num_opcodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern const struct powerpc_opcode vle_opcodes[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern const int vle_num_opcodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Values defined for the flags field of a struct powerpc_opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Opcode is defined for the PowerPC architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PPC_OPCODE_PPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Opcode is defined for the POWER (RS/6000) architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PPC_OPCODE_POWER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Opcode is defined for the POWER2 (Rios 2) architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PPC_OPCODE_POWER2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) but it also supports many additional POWER instructions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PPC_OPCODE_601 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Opcode is supported in both the Power and PowerPC architectures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (ie, compiler's -mcpu=common or assembler's -mcom). More than just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) and PPC_OPCODE_POWER2 because many instructions changed mnemonics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) between POWER and POWERPC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PPC_OPCODE_COMMON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Opcode is supported for any Power or PowerPC platform (this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) for the assembler's -many option, and it eliminates duplicates). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PPC_OPCODE_ANY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Opcode is only defined on 64 bit architectures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PPC_OPCODE_64 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Opcode is supported as part of the 64-bit bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PPC_OPCODE_64_BRIDGE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Opcode is supported by Altivec Vector Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PPC_OPCODE_ALTIVEC 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Opcode is supported by PowerPC 403 processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PPC_OPCODE_403 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Opcode is supported by PowerPC BookE processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PPC_OPCODE_BOOKE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Opcode is supported by PowerPC 440 processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PPC_OPCODE_440 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Opcode is only supported by Power4 architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PPC_OPCODE_POWER4 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Opcode is only supported by Power7 architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PPC_OPCODE_POWER7 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Opcode is only supported by e500x2 Core. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PPC_OPCODE_SPE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Opcode is supported by e500x2 Integer select APU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PPC_OPCODE_ISEL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Opcode is an e500 SPE floating point instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PPC_OPCODE_EFS 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Opcode is supported by branch locking APU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PPC_OPCODE_BRLOCK 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Opcode is supported by performance monitor APU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PPC_OPCODE_PMR 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Opcode is supported by cache locking APU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PPC_OPCODE_CACHELCK 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Opcode is supported by machine check APU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PPC_OPCODE_RFMCI 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Opcode is only supported by Power5 architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PPC_OPCODE_POWER5 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Opcode is supported by PowerPC e300 family. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PPC_OPCODE_E300 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Opcode is only supported by Power6 architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PPC_OPCODE_POWER6 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Opcode is only supported by PowerPC Cell family. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PPC_OPCODE_CELL 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Opcode is supported by CPUs with paired singles support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PPC_OPCODE_PPCPS 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Opcode is supported by Power E500MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PPC_OPCODE_E500MC 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Opcode is supported by PowerPC 405 processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PPC_OPCODE_405 0x8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Opcode is supported by Vector-Scalar (VSX) Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PPC_OPCODE_VSX 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Opcode is supported by A2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PPC_OPCODE_A2 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Opcode is supported by PowerPC 476 processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PPC_OPCODE_476 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Opcode is supported by AppliedMicro Titan core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PPC_OPCODE_TITAN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Opcode which is supported by the e500 family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PPC_OPCODE_E500 0x100000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Opcode is supported by Extended Altivec Vector Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PPC_OPCODE_ALTIVEC2 0x200000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Opcode is supported by Power E6500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PPC_OPCODE_E6500 0x400000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Opcode is supported by Thread management APU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PPC_OPCODE_TMR 0x800000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Opcode which is supported by the VLE extension. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PPC_OPCODE_VLE 0x1000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Opcode is only supported by Power8 architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PPC_OPCODE_POWER8 0x2000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Opcode which is supported by the Hardware Transactional Memory extension. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Currently, this is the same as the POWER8 mask. If another cpu comes out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) that isn't a superset of POWER8, we can define this to its own mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PPC_OPCODE_HTM PPC_OPCODE_POWER8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Opcode is supported by ppc750cl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PPC_OPCODE_750 0x4000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Opcode is supported by ppc7450. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PPC_OPCODE_7450 0x8000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Opcode is supported by ppc821/850/860. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PPC_OPCODE_860 0x10000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Opcode is only supported by Power9 architecture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PPC_OPCODE_POWER9 0x20000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PPC_OPCODE_VSX3 0x40000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Opcode is supported by e200z4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PPC_OPCODE_E200Z4 0x80000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* A macro to extract the major opcode from an instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PPC_OP(i) (((i) >> 26) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* A macro to determine if the instruction is a 2-byte VLE insn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* A macro to extract the major opcode from a VLE instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* A macro to convert a VLE opcode to a VLE opcode segment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VLE_OP_TO_SEG(i) ((i) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* The operands table is an array of struct powerpc_operand. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct powerpc_operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* A bitmask of bits in the operand. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int bitm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* The shift operation to be applied to the operand. No shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) is made if this is zero. For positive values, the operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) is shifted left by SHIFT. For negative values, the operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) that BITM and SHIFT cannot be used to determine where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) operand goes in the insn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Insertion function. This is used by the assembler. To insert an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) operand value into an instruction, check this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) If it is NULL, execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (o->shift >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) i |= (op & o->bitm) << o->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) i |= (op & o->bitm) >> -o->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (i is the instruction which we are filling in, o is a pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) this structure, and op is the operand value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) If this field is not NULL, then simply call it with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) instruction and the operand value. It will return the new value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) of the instruction. If the ERRMSG argument is not NULL, then if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) the operand value is illegal, *ERRMSG will be set to a warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) string (the operand will be inserted in any case). If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) operand value is legal, *ERRMSG will be unchanged (most operands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) can accept any value). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long (*insert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Extraction function. This is used by the disassembler. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) extract this operand type from an instruction, check this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) If it is NULL, compute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (o->shift >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) op = (i >> o->shift) & o->bitm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) op = (i << -o->shift) & o->bitm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if ((o->flags & PPC_OPERAND_SIGNED) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sign_extend (op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (i is the instruction, o is a pointer to this structure, and op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) is the result).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) If this field is not NULL, then simply call it with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) instruction value. It will return the value of the operand. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) the INVALID argument is not NULL, *INVALID will be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) non-zero if this operand type can not actually be extracted from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) this operand (i.e., the instruction does not match). If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) operand is valid, *INVALID will not be changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* One bit syntax flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Elements in the table are retrieved by indexing with values from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) the operands field of the powerpc_opcodes table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) extern const struct powerpc_operand powerpc_operands[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) extern const unsigned int num_powerpc_operands;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Use with the shift field of a struct powerpc_operand to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) that BITM and SHIFT cannot be used to determine where the operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) goes in the insn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PPC_OPSHIFT_INV (-1U << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Values defined for the flags field of a struct powerpc_operand. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* This operand takes signed values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PPC_OPERAND_SIGNED (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* This operand takes signed values, but also accepts a full positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) range of values when running in 32 bit mode. That is, if bits is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) this flag is ignored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define PPC_OPERAND_SIGNOPT (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* This operand does not actually exist in the assembler input. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) is used to support extended mnemonics such as mr, for which two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) operands fields are identical. The assembler should call the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) insert function with any op value. The disassembler should call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) the extract function, ignore the return value, and check the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) placed in the valid argument. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PPC_OPERAND_FAKE (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* The next operand should be wrapped in parentheses rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) separated from this one by a comma. This is used for the load and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) store instructions which want their operands to look like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg,displacement(reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PPC_OPERAND_PARENS (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* This operand may use the symbolic names for the CR fields, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) lt 0 gt 1 eq 2 so 3 un 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cr0 0 cr1 1 cr2 2 cr3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cr4 4 cr5 5 cr6 6 cr7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) These may be combined arithmetically, as in cr2*4+gt. These are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) only supported on the PowerPC, not the POWER. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PPC_OPERAND_CR_BIT (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* This operand names a register. The disassembler uses this to print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) register names with a leading 'r'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PPC_OPERAND_GPR (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PPC_OPERAND_GPR_0 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* This operand names a floating point register. The disassembler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) prints these with a leading 'f'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PPC_OPERAND_FPR (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* This operand is a relative branch displacement. The disassembler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) prints these symbolically if possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PPC_OPERAND_RELATIVE (0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* This operand is an absolute branch address. The disassembler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) prints these symbolically if possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PPC_OPERAND_ABSOLUTE (0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* This operand is optional, and is zero if omitted. This is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) example, in the optional BF field in the comparison instructions. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) assembler must count the number of operands remaining on the line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) and the number of operands remaining for the opcode, and decide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) whether this operand is present or not. The disassembler should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) print this operand out only if it is not zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PPC_OPERAND_OPTIONAL (0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) is omitted, then for the next operand use this operand value plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 1, ignoring the next operand field for the opcode. This wretched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hack is needed because the Power rotate instructions can take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) either 4 or 5 operands. The disassembler should print this operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) out regardless of the PPC_OPERAND_OPTIONAL field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PPC_OPERAND_NEXT (0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* This operand should be regarded as a negative number for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) purposes of overflow checking (i.e., the normal most negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) number is disallowed and one more than the normal most positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) number is allowed). This flag will only be set for a signed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) operand. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PPC_OPERAND_NEGATIVE (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* This operand names a vector unit register. The disassembler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) prints these with a leading 'v'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PPC_OPERAND_VR (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* This operand is for the DS field in a DS form instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PPC_OPERAND_DS (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* This operand is for the DQ field in a DQ form instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PPC_OPERAND_DQ (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Valid range of operand is 0..n rather than 0..n-1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PPC_OPERAND_PLUS1 (0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Xilinx APU and FSL related operands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PPC_OPERAND_FSL (0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PPC_OPERAND_FCR (0x40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PPC_OPERAND_UDI (0x80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* This operand names a vector-scalar unit register. The disassembler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) prints these with a leading 'vs'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PPC_OPERAND_VSR (0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* This is a CR FIELD that does not use symbolic names. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PPC_OPERAND_CR_REG (0x200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) is omitted, then the value it should use for the operand is stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) in the SHIFT field of the immediatly following operand field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) only optional when generating 32-bit code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PPC_OPERAND_OPTIONAL32 (0x800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* The POWER and PowerPC assemblers use a few macros. We keep them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) with the operands table for simplicity. The macro table is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) array of struct powerpc_macro. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct powerpc_macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* The macro name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* The number of operands the macro takes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int operands;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* One bit flags for the opcode. These are used to indicate which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) specific processors support the instructions. The values are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) same as those for the struct powerpc_opcode flags field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ppc_cpu_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* A format string to turn the macro into a normal instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Each %N in the string is replaced with operand number N (zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) based). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const char *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) extern const struct powerpc_macro powerpc_macros[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) extern const int powerpc_num_macros;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ppc_optional_operand_value (const struct powerpc_operand *operand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return (operand+1)->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef __cplusplus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #endif /* PPC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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