^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016,2017 IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define pr_fmt(fmt) "xive: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/libfdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/xive.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/xive-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/hvcall.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/svm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/ultravisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "xive-internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u32 xive_queue_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct xive_irq_bitmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static LIST_HEAD(xive_irq_bitmaps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int xive_irq_bitmap_add(int base, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct xive_irq_bitmap *xibm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) xibm = kzalloc(sizeof(*xibm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (!xibm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) spin_lock_init(&xibm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) xibm->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) xibm->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!xibm->bitmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) kfree(xibm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) list_add(&xibm->list, &xive_irq_bitmaps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_info("Using IRQ range [%x-%x]", xibm->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) xibm->base + xibm->count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) irq = find_first_zero_bit(xibm->bitmap, xibm->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (irq != xibm->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) set_bit(irq, xibm->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) irq += xibm->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) irq = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int xive_irq_bitmap_alloc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct xive_irq_bitmap *xibm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int irq = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spin_lock_irqsave(&xibm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irq = __xive_irq_bitmap_alloc(xibm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spin_unlock_irqrestore(&xibm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void xive_irq_bitmap_free(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct xive_irq_bitmap *xibm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) spin_lock_irqsave(&xibm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clear_bit(irq - xibm->base, xibm->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_unlock_irqrestore(&xibm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Based on the similar routines in RTAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned int plpar_busy_delay_time(long rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int ms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (H_IS_LONG_BUSY(rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ms = get_longbusy_msecs(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } else if (rc == H_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ms = 10; /* seems appropriate for XIVE hcalls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static unsigned int plpar_busy_delay(int rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ms = plpar_busy_delay_time(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mdelay(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Note: this call has a partition wide scope and can take a while to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * complete. If it returns H_LONG_BUSY_* it should be retried
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * periodically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static long plpar_int_reset(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rc = plpar_hcall_norets(H_INT_RESET, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_err("H_INT_RESET failed %ld\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static long plpar_int_get_source_info(unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long lisn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long *src_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long *eoi_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long *trig_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long *esb_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *src_flags = retbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *eoi_page = retbuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *trig_page = retbuf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *esb_shift = retbuf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static long plpar_int_set_source_config(unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long lisn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long sw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) flags, lisn, target, prio, sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) target, prio, sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) lisn, target, prio, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static long plpar_int_get_source_config(unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long lisn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long *prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long *sw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) target, prio, sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) lisn, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *target = retbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *prio = retbuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *sw_irq = retbuf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) retbuf[0], retbuf[1], retbuf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static long plpar_int_get_queue_info(unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long *esn_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long *esn_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) target, priority, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *esn_page = retbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *esn_size = retbuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) retbuf[0], retbuf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static long plpar_int_set_queue_config(unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long qpage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned long qsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) flags, target, priority, qpage, qsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) priority, qpage, qsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) target, priority, qpage, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static long plpar_int_sync(unsigned long flags, unsigned long lisn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static long plpar_int_esb(unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long lisn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long in_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long *out_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) flags, lisn, offset, in_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) in_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } while (plpar_busy_delay(rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) lisn, offset, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *out_data = retbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned long read_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) lisn, offset, data, &read_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return write ? 0 : read_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define XIVE_SRC_LSI (1ull << (63 - 61))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define XIVE_SRC_TRIGGER (1ull << (63 - 62))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long eoi_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long trig_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long esb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) memset(data, 0, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) &esb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (flags & XIVE_SRC_H_INT_ESB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (flags & XIVE_SRC_STORE_EOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (flags & XIVE_SRC_LSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->flags |= XIVE_IRQ_FLAG_LSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) data->eoi_page = eoi_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) data->esb_shift = esb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) data->trig_page = trig_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) data->hw_irq = hw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * No chip-id for the sPAPR backend. This has an impact how we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * pick a target. See xive_pick_irq_target().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) data->src_chip = XIVE_INVALID_CHIP_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * be used for interrupt management. Skip the remapping of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * ESB pages which are not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!data->eoi_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Full function page supports trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (flags & XIVE_SRC_TRIGGER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) data->trig_mmio = data->eoi_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!data->trig_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) prio, sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return rc == 0 ? 0 : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 *sw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long h_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long h_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long h_sw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) &h_sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *target = h_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *prio = h_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *sw_irq = h_sw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return rc == 0 ? 0 : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* This can be called multiple time to change a queue configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __be32 *qpage, u32 order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) s64 rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long esn_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long esn_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u64 flags, qpage_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* If there's an actual queue page, clean it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (order) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (WARN_ON(!qpage))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) qpage_phys = __pa(qpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) qpage_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Initialize the rest of the fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) q->msk = order ? ((1u << (order - 2)) - 1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) q->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) q->toggle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) target, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* TODO: add support for the notification page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) q->eoi_phys = esn_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Default is to always notify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) flags = XIVE_EQ_ALWAYS_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Configure and enable the queue in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) target, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) q->qpage = qpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (is_secure_guest())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uv_share_page(PHYS_PFN(qpage_phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 1 << xive_alloc_order(order));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct xive_q *q = &xc->queue[prio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __be32 *qpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (IS_ERR(qpage))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return PTR_ERR(qpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) q, prio, qpage, xive_queue_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct xive_q *q = &xc->queue[prio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int alloc_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int hw_cpu = get_hard_smp_processor_id(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hw_cpu, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) alloc_order = xive_alloc_order(xive_queue_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (is_secure_guest())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) free_pages((unsigned long)q->qpage, alloc_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) q->qpage = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static bool xive_spapr_match(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Ignore cascaded controllers for the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int irq = xive_irq_bitmap_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pr_err("Failed to allocate IPI on CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) xc->hw_ipi = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (xc->hw_ipi == XIVE_BAD_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) xive_irq_bitmap_free(xc->hw_ipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) xc->hw_ipi = XIVE_BAD_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void xive_spapr_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) plpar_int_reset(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * Perform an "ack" cycle on the current thread. Grab the pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * active priorities and update the CPPR to the most favored one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void xive_spapr_update_pending(struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 nsr, cppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u16 ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Perform the "Acknowledge O/S to Register" cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Let's speedup the access to the TIMA using the raw I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * accessor as we don't need the synchronisation routine of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * the higher level ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Synchronize subsequent queue accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Grab the CPPR and the "NSR" field which indicates the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * of the interrupt (if any)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cppr = ack & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) nsr = ack >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (nsr & TM_QW1_NSR_EO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (cppr == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Mark the priority pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) xc->pending_prio |= 1 << cppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * A new interrupt should never have a CPPR less favored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * than our current one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (cppr >= xc->cppr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pr_err("CPU %d odd ack CPPR, got %d at %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) smp_processor_id(), cppr, xc->cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Update our idea of what the CPPR is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) xc->cppr = cppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static void xive_spapr_eoi(u32 hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Not used */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Only some debug on the TIMA settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pr_debug("(HW value: %08x %08x %08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Nothing to do */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void xive_spapr_sync_source(u32 hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Specs are unclear on what this is doing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) plpar_int_sync(0, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int xive_spapr_debug_show(struct seq_file *m, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct xive_irq_bitmap *xibm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) memset(buf, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) bitmap_print_to_pagebuf(true, buf, xibm->bitmap, xibm->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) seq_printf(m, "bitmap #%d: %s", xibm->count, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct xive_ops xive_spapr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .populate_irq_data = xive_spapr_populate_irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .configure_irq = xive_spapr_configure_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .get_irq_config = xive_spapr_get_irq_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .setup_queue = xive_spapr_setup_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .cleanup_queue = xive_spapr_cleanup_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .match = xive_spapr_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .shutdown = xive_spapr_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .update_pending = xive_spapr_update_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .eoi = xive_spapr_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .setup_cpu = xive_spapr_setup_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .teardown_cpu = xive_spapr_teardown_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .sync_source = xive_spapr_sync_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .esb_rw = xive_spapr_esb_rw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .get_ipi = xive_spapr_get_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .put_ipi = xive_spapr_put_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .debug_show = xive_spapr_debug_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .name = "spapr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * get max priority from "/ibm,plat-res-int-priorities"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static bool xive_get_max_prio(u8 *max_prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct device_node *rootdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) const __be32 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int prio, found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rootdn = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!rootdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pr_err("not root node found !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (len % (2 * sizeof(u32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* HW supports priorities in the range [0-7] and 0xFF is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * wildcard priority used to mask. We scan the ranges reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * by the hypervisor to find the lowest priority we can use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) found = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) for (prio = 0; prio < 8; prio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) for (i = 0; i < len / (2 * sizeof(u32)); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int base = be32_to_cpu(reg[2 * i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int range = be32_to_cpu(reg[2 * i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (prio >= base && prio < base + range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) reserved++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) found = prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (found == 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *max_prio = found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const u8 *get_vec5_feature(unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned long root, chosen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) const u8 *vec5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) root = of_get_flat_dt_root();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (chosen == -FDT_ERR_NOTFOUND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!vec5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (size <= index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return vec5 + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static bool __init xive_spapr_disabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) const u8 *vec5_xive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (vec5_xive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case OV5_FEAT(OV5_XIVE_EITHER):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case OV5_FEAT(OV5_XIVE_LEGACY):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case OV5_FEAT(OV5_XIVE_EXPLOIT):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Hypervisor only supports XIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (xive_cmdline_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pr_warn("WARNING: Ignoring cmdline option xive=off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pr_warn("%s: Unknown xive support option: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return xive_cmdline_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bool __init xive_spapr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) void __iomem *tima;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u8 max_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) const __be32 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (xive_spapr_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pr_devel("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) pr_devel("not found !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pr_devel("Found %s\n", np->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Resource 1 is the OS ring TIMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (of_address_to_resource(np, 1, &r)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pr_err("Failed to get thread mgmnt area resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) tima = ioremap(r.start, resource_size(&r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!tima) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pr_err("Failed to map thread mgmnt area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!xive_get_max_prio(&max_prio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Feed the IRQ number allocator with the ranges given in the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (len % (2 * sizeof(u32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) xive_irq_bitmap_add(be32_to_cpu(reg[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) be32_to_cpu(reg[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Iterate the EQ sizes and pick one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) xive_queue_shift = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (val == PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Initialize XIVE core with our backend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) machine_arch_initcall(pseries, xive_core_debug_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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