^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016,2017 IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define pr_fmt(fmt) "xive: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kmemleak.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/xive.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/xive-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/opal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/kvm_ppc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "xive-internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u32 xive_provision_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static u32 *xive_provision_chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u32 xive_provision_chip_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static u32 xive_queue_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static u32 xive_pool_vps = XIVE_INVALID_VP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct kmem_cache *xive_provision_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static bool xive_has_single_esc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __be64 flags, eoi_page, trig_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __be32 esb_shift, src_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u64 opal_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) memset(data, 0, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) &esb_shift, &src_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) hw_irq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) opal_flags = be64_to_cpu(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (opal_flags & OPAL_XIVE_IRQ_LSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) data->flags |= XIVE_IRQ_FLAG_LSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) data->flags |= XIVE_IRQ_FLAG_MASK_FW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) data->flags |= XIVE_IRQ_FLAG_EOI_FW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) data->eoi_page = be64_to_cpu(eoi_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) data->trig_page = be64_to_cpu(trig_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) data->esb_shift = be32_to_cpu(esb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) data->src_chip = be32_to_cpu(src_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!data->eoi_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) data->hw_irq = hw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!data->trig_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (data->trig_page == data->eoi_page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) data->trig_mmio = data->eoi_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!data->trig_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return rc == 0 ? 0 : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXPORT_SYMBOL_GPL(xive_native_configure_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 *sw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __be64 vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __be32 lirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *target = be64_to_cpu(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *sw_irq = be32_to_cpu(lirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return rc == 0 ? 0 : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* This can be called multiple time to change a queue configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __be32 *qpage, u32 order, bool can_escalate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) s64 rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __be64 qeoi_page_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __be32 esc_irq_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u64 flags, qpage_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* If there's an actual queue page, clean it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (order) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (WARN_ON(!qpage))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) qpage_phys = __pa(qpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) qpage_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Initialize the rest of the fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) q->msk = order ? ((1u << (order - 2)) - 1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) q->idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) q->toggle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) &qeoi_page_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &esc_irq_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pr_err("Error %lld getting queue info prio %d\n", rc, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) q->eoi_phys = be64_to_cpu(qeoi_page_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Default flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Escalation needed ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (can_escalate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) q->esc_irq = be32_to_cpu(esc_irq_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) flags |= OPAL_XIVE_EQ_ESCALATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Configure and enable the queue in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pr_err("Error %lld setting queue for prio %d\n", rc, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * KVM code requires all of the above to be visible before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * q->qpage is set due to how it manages IPI EOIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) q->qpage = qpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) EXPORT_SYMBOL_GPL(xive_native_configure_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Disable the queue in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __xive_native_disable_queue(vp_id, q, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) EXPORT_SYMBOL_GPL(xive_native_disable_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct xive_q *q = &xc->queue[prio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __be32 *qpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ERR(qpage))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PTR_ERR(qpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) q, prio, qpage, xive_queue_shift, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct xive_q *q = &xc->queue[prio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int alloc_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * We use the variant with no iounmap as this is called on exec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * from an IPI and iounmap isn't safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) alloc_order = xive_alloc_order(xive_queue_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) free_pages((unsigned long)q->qpage, alloc_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) q->qpage = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static bool xive_native_match(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return of_device_is_compatible(node, "ibm,opal-xive-vc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static s64 opal_xive_allocate_irq(u32 chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) s64 irq = opal_xive_allocate_irq_raw(chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Old versions of skiboot can incorrectly return 0xffffffff to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * indicate no space, fix it up here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return irq == 0xffffffff ? OPAL_RESOURCE : irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) s64 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Allocate an IPI and populate info about it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) irq = opal_xive_allocate_irq(xc->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (irq == OPAL_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pr_err("Failed to allocate IPI on CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) xc->hw_ipi = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 xive_native_alloc_irq_on_chip(u32 chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rc = opal_xive_allocate_irq(chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void xive_native_free_irq(u32 irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) s64 rc = opal_xive_free_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) EXPORT_SYMBOL_GPL(xive_native_free_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Free the IPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (xc->hw_ipi == XIVE_BAD_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rc = opal_xive_free_irq(xc->hw_ipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (rc == OPAL_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) xc->hw_ipi = XIVE_BAD_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void xive_native_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Switch the XIVE to emulation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) opal_xive_reset(OPAL_XIVE_MODE_EMU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Perform an "ack" cycle on the current thread, thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * grabbing the pending active priorities and updating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * the CPPR to the most favored one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void xive_native_update_pending(struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 he, cppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u16 ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Perform the acknowledge hypervisor to register cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Synchronize subsequent queue accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Grab the CPPR and the "HE" field which indicates the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * of the hypervisor interrupt (if any)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cppr = ack & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) he = (ack >> 8) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch(he) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (cppr == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Mark the priority pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) xc->pending_prio |= 1 << cppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * A new interrupt should never have a CPPR less favored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * than our current one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (cppr >= xc->cppr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pr_err("CPU %d odd ack CPPR, got %d at %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) smp_processor_id(), cppr, xc->cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Update our idea of what the CPPR is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) xc->cppr = cppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pr_err("CPU %d got unexpected interrupt type HE=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) smp_processor_id(), he);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void xive_native_eoi(u32 hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Not normally used except if specific interrupts need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * a workaround on EOI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) opal_int_eoi(hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __be64 vp_cam_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u64 vp_cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (xive_pool_vps == XIVE_INVALID_VP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Check if pool VP already active, if it is, pull it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Enable the pool VP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) vp = xive_pool_vps + cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pr_err("Failed to enable pool VP on CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Grab it's CAM value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pr_err("Failed to get pool VP info CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) vp_cam = be64_to_cpu(vp_cam_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (xive_pool_vps == XIVE_INVALID_VP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Pull the pool VP from the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) vp = xive_pool_vps + cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rc = opal_xive_set_vp_info(vp, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void xive_native_sync_source(u32 hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) EXPORT_SYMBOL_GPL(xive_native_sync_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void xive_native_sync_queue(u32 hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) EXPORT_SYMBOL_GPL(xive_native_sync_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct xive_ops xive_native_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .populate_irq_data = xive_native_populate_irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .configure_irq = xive_native_configure_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .get_irq_config = xive_native_get_irq_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .setup_queue = xive_native_setup_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .cleanup_queue = xive_native_cleanup_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .match = xive_native_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .shutdown = xive_native_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .update_pending = xive_native_update_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .eoi = xive_native_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .setup_cpu = xive_native_setup_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .teardown_cpu = xive_native_teardown_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .sync_source = xive_native_sync_source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .get_ipi = xive_native_get_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .put_ipi = xive_native_put_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "native",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static bool xive_parse_provisioning(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (of_property_read_u32(np, "ibm,xive-provision-page-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &xive_provision_size) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pr_err("Error %d getting provision chips array\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) xive_provision_chip_count = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) xive_provision_chips = kcalloc(4, xive_provision_chip_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (WARN_ON(!xive_provision_chips))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) xive_provision_chips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) xive_provision_chip_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pr_err("Error %d reading provision chips array\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) xive_provision_cache = kmem_cache_create("xive-provision",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) xive_provision_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) xive_provision_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!xive_provision_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pr_err("Failed to allocate provision cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void xive_native_setup_pools(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Allocate a pool big enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) xive_pool_vps, nr_cpu_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 xive_native_default_eq_shift(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return xive_queue_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long xive_tima_os;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) EXPORT_SYMBOL_GPL(xive_tima_os);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) bool __init xive_native_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) void __iomem *tima;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 max_prio = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 val, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (xive_cmdline_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pr_devel("xive_native_init()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pr_devel("not found !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pr_devel("Found %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Resource 1 is HV window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (of_address_to_resource(np, 1, &r)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pr_err("Failed to get thread mgmnt area resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) tima = ioremap(r.start, resource_size(&r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!tima) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pr_err("Failed to map thread mgmnt area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Read number of priorities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) max_prio = val - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Iterate the EQ sizes and pick one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) xive_queue_shift = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (val == PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Do we support single escalation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (of_get_property(np, "single-escalation-support", NULL) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) xive_has_single_esc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Configure Thread Management areas for KVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) kvmppc_set_xive_tima(cpu, r.start, tima);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Resource 2 is OS window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (of_address_to_resource(np, 2, &r)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pr_err("Failed to get thread mgmnt area resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) xive_tima_os = r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Grab size of provisionning pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) xive_parse_provisioning(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Switch the XIVE to exploitation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) pr_err("Switch to exploitation mode failed with error %lld\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Setup some dummy HV pool VPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) xive_native_setup_pools();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Initialize XIVE core with our backend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) max_prio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) opal_xive_reset(OPAL_XIVE_MODE_EMU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static bool xive_native_provision_pages(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) for (i = 0; i < xive_provision_chip_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 chip = xive_provision_chips[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * XXX TODO: Try to make the allocation local to the node where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * the chip resides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pr_err("Failed to allocate provisioning page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) kmemleak_ignore(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) opal_xive_donate_page(chip, __pa(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 xive_native_alloc_vp_block(u32 max_vcpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) order = fls(max_vcpus) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (max_vcpus > (1 << order))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) order++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) max_vcpus, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) rc = opal_xive_alloc_vp_block(order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) switch (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case OPAL_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case OPAL_XIVE_PROVISIONING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!xive_native_provision_pages())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return XIVE_INVALID_VP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) order, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return XIVE_INVALID_VP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void xive_native_free_vp_block(u32 vp_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (vp_base == XIVE_INVALID_VP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) rc = opal_xive_free_vp_block(vp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pr_warn("OPAL error %lld freeing VP block\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int xive_native_enable_vp(u32 vp_id, bool single_escalation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u64 flags = OPAL_XIVE_VP_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (single_escalation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) flags |= OPAL_XIVE_VP_SINGLE_ESCALATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rc = opal_xive_set_vp_info(vp_id, flags, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return rc ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) EXPORT_SYMBOL_GPL(xive_native_enable_vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int xive_native_disable_vp(u32 vp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) rc = opal_xive_set_vp_info(vp_id, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (rc != OPAL_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) msleep(OPAL_BUSY_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return rc ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) EXPORT_SYMBOL_GPL(xive_native_disable_vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __be64 vp_cam_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __be32 vp_chip_id_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *out_chip_id = be32_to_cpu(vp_chip_id_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) EXPORT_SYMBOL_GPL(xive_native_get_vp_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bool xive_native_has_single_escalation(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return xive_has_single_esc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int xive_native_get_queue_info(u32 vp_id, u32 prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u64 *out_qpage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u64 *out_qsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u64 *out_qeoi_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 *out_escalate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u64 *out_qflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __be64 qpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __be64 qsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __be64 qeoi_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __be32 escalate_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __be64 qflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) &qeoi_page, &escalate_irq, &qflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) vp_id, prio, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (out_qpage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) *out_qpage = be64_to_cpu(qpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (out_qsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *out_qsize = be32_to_cpu(qsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (out_qeoi_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *out_qeoi_page = be64_to_cpu(qeoi_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (out_escalate_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *out_escalate_irq = be32_to_cpu(escalate_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (out_qflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *out_qflags = be64_to_cpu(qflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) EXPORT_SYMBOL_GPL(xive_native_get_queue_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __be32 opal_qtoggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) __be32 opal_qindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) &opal_qindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) vp_id, prio, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (qtoggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *qtoggle = be32_to_cpu(opal_qtoggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (qindex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *qindex = be32_to_cpu(opal_qindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) EXPORT_SYMBOL_GPL(xive_native_get_queue_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) vp_id, prio, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) EXPORT_SYMBOL_GPL(xive_native_set_queue_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) bool xive_native_has_queue_state_support(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return opal_check_token(OPAL_XIVE_GET_QUEUE_STATE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) opal_check_token(OPAL_XIVE_SET_QUEUE_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) EXPORT_SYMBOL_GPL(xive_native_has_queue_state_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __be64 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) s64 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) rc = opal_xive_get_vp_state(vp_id, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pr_err("OPAL failed to get vp state for VCPU %d : %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) vp_id, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (out_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) *out_state = be64_to_cpu(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) EXPORT_SYMBOL_GPL(xive_native_get_vp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) machine_arch_initcall(powernv, xive_core_debug_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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