Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2011 IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/rtas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/xics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Globals common to all ICP/ICS implementations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) const struct icp_ops	*icp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) unsigned int xics_default_server		= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) unsigned int xics_default_distrib_server	= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) unsigned int xics_interrupt_server_size		= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct irq_domain *xics_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static LIST_HEAD(ics_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) void xics_update_irq_servers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 ilen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	const __be32 *ireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 hcpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* Find the server numbers for the boot cpu. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	np = of_get_cpu_node(boot_cpuid, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	BUG_ON(!np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	hcpuid = get_hard_smp_processor_id(boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	xics_default_server = xics_default_distrib_server = hcpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (!ireg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	i = ilen / sizeof(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* Global interrupt distribution server is specified in the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * entry fom this property for current boot cpu id and use it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * default distribution server
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	for (j = 0; j < i; j += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		if (be32_to_cpu(ireg[j]) == hcpuid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	pr_devel("xics: xics_default_distrib_server = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		 xics_default_distrib_server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* GIQ stuff, currently only supported on RTAS setups, will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * to be sorted properly for bare metal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #ifdef CONFIG_PPC_RTAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	index = (1UL << xics_interrupt_server_size) - 1 - gserver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	     GLOBAL_INTERRUPT_QUEUE, index, join, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void xics_setup_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	icp_ops->set_priority(LOWEST_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	xics_set_cpu_giq(xics_default_distrib_server, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void xics_mask_unknown_vec(unsigned int vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct ics *ics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	list_for_each_entry(ics, &ics_list, link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		ics->mask_unknown(ics, vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void xics_request_ipi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned int ipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ipi = irq_create_mapping(xics_host, XICS_IPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	BUG_ON(!ipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * IPIs are marked IRQF_PERCPU. The handler was set in map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	BUG_ON(request_irq(ipi, icp_ops->ipi_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			   IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __init xics_smp_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Register all the IPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	xics_request_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* Setup cause_ipi callback based on which ICP is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	smp_ops->cause_ipi = icp_ops->cause_ipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void xics_teardown_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * we have to reset the cppr index to 0 because we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * not going to return from the IPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	os_cppr->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	icp_ops->set_priority(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	icp_ops->teardown_cpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void xics_kexec_teardown_cpu(int secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	xics_teardown_cpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	icp_ops->flush_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 * Some machines need to have at least one cpu in the GIQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * so leave the master cpu in the group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		xics_set_cpu_giq(xics_default_distrib_server, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Interrupts are disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void xics_migrate_irqs_away(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned int irq, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct irq_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* If we used to be the default server, move to the new "boot_cpuid" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (hw_cpu == xics_default_server)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		xics_update_irq_servers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Reject any interrupt that was queued to us... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	icp_ops->set_priority(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Remove ourselves from the global interrupt queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	xics_set_cpu_giq(xics_default_distrib_server, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	for_each_irq_desc(virq, desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		long server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		struct ics *ics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/* We can't set affinity on ISA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (virq < NUM_ISA_INTERRUPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		/* We only need to migrate enabled IRQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (!desc->action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (desc->irq_data.domain != xics_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		irq = desc->irq_data.hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		/* We need to get IPIs still. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (!chip || !chip->irq_set_affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		/* Locate interrupt server */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		server = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		ics = irq_desc_get_chip_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (ics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			server = ics->get_server(ics, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if (server < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			printk(KERN_ERR "%s: Can't find server for irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			       __func__, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		/* We only support delivery to all cpus or to one cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		 * The irq has to be migrated only in the single cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		 * case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (server != hw_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		/* This is expected during cpu offline. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (cpu_online(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			pr_warn("IRQ %u affinity broken off cpu %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				virq, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		/* Reset affinity to all cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		irq_set_affinity(virq, cpu_all_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Allow "sufficient" time to drop any inflight IRQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * Allow IPIs again. This is done at the very end, after migrating all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * interrupts, the expectation is that we'll only get woken up by an IPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * interrupt beyond this point, but leave externals masked just to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * safe. If we're using icp-opal this may actually allow all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 * interrupts anyway, but that should be OK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	icp_ops->set_priority(DEFAULT_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * For the moment we only implement delivery to all cpus or one cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * If the requested affinity is cpu_all_mask, we set global affinity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * If not we set it to the first cpu in the mask, even if multiple cpus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * are set. This is so things like irqbalance (which set core and package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * wide affinities) do the right thing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * We need to fix this to implement support for the links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			unsigned int strict_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!distribute_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return xics_default_server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (!cpumask_subset(cpu_possible_mask, cpumask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		int server = cpumask_first_and(cpu_online_mask, cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (server < nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			return get_hard_smp_processor_id(server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (strict_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * Workaround issue with some versions of JS20 firmware that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * deliver interrupts to cpus which haven't been started. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 * happens when using the maxcpus= boot option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (cpumask_equal(cpu_online_mask, cpu_present_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return xics_default_distrib_server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return xics_default_server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int xics_host_match(struct irq_domain *h, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			   enum irq_domain_bus_token bus_token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct ics *ics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	list_for_each_entry(ics, &ics_list, link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if (ics->host_match(ics, node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Dummies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void xics_ipi_unmask(struct irq_data *d) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void xics_ipi_mask(struct irq_data *d) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct irq_chip xics_ipi_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.name = "XICS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.irq_eoi = NULL, /* Patched at init time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.irq_mask = xics_ipi_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.irq_unmask = xics_ipi_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int xics_host_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			 irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct ics *ics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	 * Mark interrupts as edge sensitive by default so that resend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	 * actually works. The device-tree parsing will turn the LSIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * back to level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	irq_clear_status_flags(virq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	/* Don't call into ICS for IPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (hw == XICS_IPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		irq_set_chip_and_handler(virq, &xics_ipi_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 					 handle_percpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/* Let the ICS setup the chip data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	list_for_each_entry(ics, &ics_list, link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (ics->map(ics, virq) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			   const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	*out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * If intsize is at least 2, we look for the type in the second cell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * we assume the LSB indicates a level interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (intsize > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		if (intspec[1] & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			*out_flags = IRQ_TYPE_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			*out_flags = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		*out_flags = IRQ_TYPE_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int xics_set_irq_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	 * We only support these. This has really no effect other than setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	 * the corresponding descriptor bits mind you but those will in turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	 * affect the resend function when re-enabling an edge interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	 * Set set the default to edge as explained in map().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		flow_type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (flow_type != IRQ_TYPE_EDGE_RISING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	    flow_type != IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	irqd_set_trigger_type(d, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	return IRQ_SET_MASK_OK_NOCOPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int xics_retrigger(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	 * We need to push a dummy CPPR when retriggering, since the subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	 * EOI will try to pop it. Passing 0 works, as the function hard codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	 * the priority value anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	xics_push_cppr(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	/* Tell the core to do a soft retrigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct irq_domain_ops xics_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	.match = xics_host_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.map = xics_host_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.xlate = xics_host_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void __init xics_init_host(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	BUG_ON(xics_host == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	irq_set_default_host(xics_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void __init xics_register_ics(struct ics *ics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	list_add(&ics->link, &ics_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void __init xics_get_server_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	const __be32 *isize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	/* We fetch the interrupt server size from the first ICS node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	 * we find if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	if (isize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		xics_interrupt_server_size = be32_to_cpu(*isize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) void __init xics_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	int rc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	/* Fist locate ICP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	if (firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		rc = icp_hv_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		rc = icp_native_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		if (rc == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		    rc = icp_opal_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		pr_warn("XICS: Cannot find a Presentation Controller !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	/* Copy get_irq callback over to ppc_md */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	ppc_md.get_irq = icp_ops->get_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	/* Patch up IPI chip EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	xics_ipi_chip.irq_eoi = icp_ops->eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	/* Now locate ICS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	rc = ics_rtas_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		rc = ics_opal_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		pr_warn("XICS: Cannot find a Source Controller !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	/* Initialize common bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	xics_get_server_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	xics_update_irq_servers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	xics_init_host();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	xics_setup_cpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }