^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ICS backend for OPAL managed interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/xics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/opal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int ics_opal_mangle_server(int server)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* No link for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return server << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int ics_opal_unmangle_server(int server)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* No link for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return server >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void ics_opal_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) server = ics_opal_mangle_server(server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (rc != OPAL_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) " error %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __func__, d->irq, hw_irq, server, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned int ics_opal_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The generic MSI code returns with the interrupt disabled on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * card, using the MSI mask bits. Firmware doesn't appear to unmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * at that level, so we do it here by hand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (irq_data_get_msi_desc(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci_msi_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* unmask it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ics_opal_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void ics_opal_mask_real_irq(unsigned int hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int server = ics_opal_mangle_server(xics_default_server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (hw_irq == XICS_IPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Have to set XIVE to 0xff to be able to remove a slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) rc = opal_set_xive(hw_irq, server, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (rc != OPAL_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __func__, hw_irq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void ics_opal_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ics_opal_mask_real_irq(hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int ics_opal_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct cpumask *cpumask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __be16 oserver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int16_t server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int8_t priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int wanted_server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rc = opal_get_xive(hw_irq, &oserver, &priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rc != OPAL_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __func__, d->irq, hw_irq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) server = be16_to_cpu(oserver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (wanted_server < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __func__, cpumask_pr_args(cpumask), d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) server = ics_opal_mangle_server(wanted_server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pr_devel("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) d->irq, hw_irq, wanted_server, server);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rc = opal_set_xive(hw_irq, server, priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (rc != OPAL_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) " error %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __func__, d->irq, hw_irq, server, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct irq_chip ics_opal_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "OPAL ICS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .irq_startup = ics_opal_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .irq_mask = ics_opal_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .irq_unmask = ics_opal_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_eoi = NULL, /* Patched at init time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .irq_set_affinity = ics_opal_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .irq_set_type = xics_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .irq_retrigger = xics_retrigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ics_opal_map(struct ics *ics, unsigned int virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static long ics_opal_get_server(struct ics *ics, unsigned long vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int ics_opal_host_match(struct ics *ics, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Only one global & state struct ics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct ics ics_hal = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .map = ics_opal_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .mask_unknown = ics_opal_mask_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .get_server = ics_opal_get_server,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .host_match = ics_opal_host_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int ics_opal_map(struct ics *ics, unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __be16 server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int8_t priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Check if HAL knows about this interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rc = opal_get_xive(hw_irq, &server, &priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (rc != OPAL_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) irq_set_chip_and_handler(virq, &ics_opal_irq_chip, handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) irq_set_chip_data(virq, &ics_hal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __be16 server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int8_t priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Check if HAL knows about this interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rc = opal_get_xive(vec, &server, &priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (rc != OPAL_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ics_opal_mask_real_irq(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static long ics_opal_get_server(struct ics *ics, unsigned long vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __be16 server;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int8_t priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Check if HAL knows about this interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rc = opal_get_xive(vec, &server, &priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (rc != OPAL_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ics_opal_unmangle_server(be16_to_cpu(server));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int __init ics_opal_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!firmware_has_feature(FW_FEATURE_OPAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* We need to patch our irq chip's EOI to point to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * right ICP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Register ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) xics_register_ics(&ics_hal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_info("ICS OPAL backend registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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