^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016 IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/xics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/opal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/kvm_ppc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void icp_opal_teardown_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int hw_cpu = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Clear any pending IPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) opal_int_set_mfrr(hw_cpu, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void icp_opal_flush_ipi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * We take the ipi irq but and never return so we need to EOI the IPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * but want to leave our priority 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Should we check all the other interrupts too?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Should we be flagging idle loop instead?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Or creating some task to be scheduled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) force_external_irq_replay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static unsigned int icp_opal_get_xirr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int kvm_xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __be32 hw_xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Handle an interrupt latched by KVM first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) kvm_xirr = kvmppc_get_xics_latch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (kvm_xirr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return kvm_xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Then ask OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) rc = opal_int_get_xirr(&hw_xirr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return be32_to_cpu(hw_xirr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static unsigned int icp_opal_get_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) xirr = icp_opal_get_xirr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) vec = xirr & 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (vec == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) irq = irq_find_mapping(xics_host, vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (likely(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) xics_push_cppr(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* We don't have a linux mapping, so have rtas mask it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) xics_mask_unknown_vec(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* We might learn about it later, so EOI it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (opal_int_eoi(xirr) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) force_external_irq_replay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void icp_opal_set_cpu_priority(unsigned char cppr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Here be dragons. The caller has asked to allow only IPI's and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * external interrupts. But OPAL XIVE doesn't support that. So instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * of allowing no interrupts allow all. That's still not right, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * currently the only caller who does this is xics_migrate_irqs_away()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * and it works in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (cppr >= DEFAULT_PRIORITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cppr = LOWEST_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) xics_set_base_cppr(cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) opal_int_set_cppr(cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) iosync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void icp_opal_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int64_t rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iosync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rc = opal_int_eoi((xics_pop_cppr() << 24) | hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * EOI tells us whether there are more interrupts to fetch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Some HW implementations might not be able to send us another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * external interrupt in that case, so we force a replay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (rc > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) force_external_irq_replay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void icp_opal_cause_ipi(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int hw_cpu = get_hard_smp_processor_id(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) kvmppc_set_host_ipi(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) opal_int_set_mfrr(hw_cpu, IPI_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static irqreturn_t icp_opal_ipi_action(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) kvmppc_clear_host_ipi(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return smp_ipi_demux();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Called when an interrupt is received on an off-line CPU to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * clear the interrupt, so that the CPU can go back to nap mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void icp_opal_flush_interrupt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) xirr = icp_opal_get_xirr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) vec = xirr & 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (vec == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (vec == XICS_IPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Clear pending IPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) kvmppc_clear_host_ipi(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pr_err("XICS: hw interrupt 0x%x to offline cpu, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "disabling\n", vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) xics_mask_unknown_vec(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* EOI the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } while (opal_int_eoi(xirr) > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct icp_ops icp_opal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .get_irq = icp_opal_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .eoi = icp_opal_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .set_priority = icp_opal_set_cpu_priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .teardown_cpu = icp_opal_teardown_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flush_ipi = icp_opal_flush_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .ipi_action = icp_opal_ipi_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .cause_ipi = icp_opal_cause_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int icp_opal_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) np = of_find_compatible_node(NULL, NULL, "ibm,opal-intc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) icp_ops = &icp_opal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) printk("XICS: Using OPAL ICP fallbacks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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