Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2011 IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/xics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/kvm_ppc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/dbell.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct icp_ipl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		u8 bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	} xirr_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		u8 bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	} xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		u8 bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	} qirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 link_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32 link_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 link_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static struct icp_ipl __iomem *icp_native_regs[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static inline unsigned int icp_native_get_xirr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* Handled an interrupt latched by KVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	xirr = kvmppc_get_xics_latch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (xirr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return xirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return in_be32(&icp_native_regs[cpu]->xirr.word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static inline void icp_native_set_xirr(unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	out_be32(&icp_native_regs[cpu]->xirr.word, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline void icp_native_set_cppr(u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	out_8(&icp_native_regs[cpu]->xirr.bytes[0], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static inline void icp_native_set_qirr(int n_cpu, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void icp_native_set_cpu_priority(unsigned char cppr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	xics_set_base_cppr(cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	icp_native_set_cppr(cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	iosync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) void icp_native_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	iosync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void icp_native_teardown_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* Clear any pending IPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	icp_native_set_qirr(cpu, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void icp_native_flush_ipi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* We take the ipi irq but and never return so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * need to EOI the IPI, but want to leave our priority 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * should we check all the other interrupts too?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * should we be flagging idle loop instead?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * or creating some task to be scheduled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	icp_native_set_xirr((0x00 << 24) | XICS_IPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static unsigned int icp_native_get_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned int xirr = icp_native_get_xirr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int vec = xirr & 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (vec == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	irq = irq_find_mapping(xics_host, vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (likely(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		xics_push_cppr(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* We don't have a linux mapping, so have rtas mask it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	xics_mask_unknown_vec(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* We might learn about it later, so EOI it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	icp_native_set_xirr(xirr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void icp_native_cause_ipi(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	kvmppc_set_host_ipi(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	icp_native_set_qirr(cpu, IPI_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void icp_native_cause_ipi_rm(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * Currently not used to send IPIs to another CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * on the same core. Only caller is KVM real mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * Need the physical address of the XICS to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * previously saved in kvm_hstate in the paca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	void __iomem *xics_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * Just like the cause_ipi functions, it is required to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * include a full barrier before causing the IPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	__raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * Called when an interrupt is received on an off-line CPU to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * clear the interrupt, so that the CPU can go back to nap mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void icp_native_flush_interrupt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	unsigned int xirr = icp_native_get_xirr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	unsigned int vec = xirr & 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (vec == XICS_IRQ_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (vec == XICS_IPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		/* Clear pending IPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		kvmppc_clear_host_ipi(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		icp_native_set_qirr(cpu, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		pr_err("XICS: hw interrupt 0x%x to offline cpu, disabling\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		       vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		xics_mask_unknown_vec(vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* EOI the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	icp_native_set_xirr(xirr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void xics_wake_cpu(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	icp_native_set_qirr(cpu, IPI_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EXPORT_SYMBOL_GPL(xics_wake_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static irqreturn_t icp_native_ipi_action(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	kvmppc_clear_host_ipi(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	icp_native_set_qirr(cpu, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return smp_ipi_demux();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init icp_native_map_one_cpu(int hw_id, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					 unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	char *rname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int i, cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* This may look gross but it's good enough for now, we don't quite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * have a hard -> linux processor id matching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	for_each_possible_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (!cpu_present(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		if (hw_id == get_hard_smp_processor_id(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			cpu = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Fail, skip that CPU. Don't print, it's normal, some XICS come up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * with way more entries in there than you have CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (cpu == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	rname = kasprintf(GFP_KERNEL, "CPU %d [0x%x] Interrupt Presentation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			  cpu, hw_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!request_mem_region(addr, size, rname)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		pr_warn("icp_native: Could not reserve ICP MMIO for CPU %d, interrupt server #0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			cpu, hw_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	icp_native_regs[cpu] = ioremap(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	kvmppc_set_xics_phys(cpu, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (!icp_native_regs[cpu]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pr_warn("icp_native: Failed ioremap for CPU %d, interrupt server #0x%x, addr %#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			cpu, hw_id, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		release_mem_region(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int __init icp_native_init_one_node(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 					   unsigned int *indx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	unsigned int ilen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	const __be32 *ireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int reg_tuple_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int num_servers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* This code does the theorically broken assumption that the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * server numbers are the same as the hard CPU numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * This happens to be the case so far but we are playing with fire...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * should be fixed one of these days. -BenH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ireg = of_get_property(np, "ibm,interrupt-server-ranges", &ilen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Do that ever happen ? we'll know soon enough... but even good'old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * f80 does have that property ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	WARN_ON((ireg == NULL) || (ilen != 2*sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (ireg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		*indx = of_read_number(ireg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		if (ilen >= 2*sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			num_servers = of_read_number(ireg + 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ireg = of_get_property(np, "reg", &ilen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!ireg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		pr_err("icp_native: Can't find interrupt reg property");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	reg_tuple_size = (of_n_addr_cells(np) + of_n_size_cells(np)) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (((ilen % reg_tuple_size) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	    || (num_servers && (num_servers != (ilen / reg_tuple_size)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		pr_err("icp_native: ICP reg len (%d) != num servers (%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		       ilen / reg_tuple_size, num_servers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	for (i = 0; i < (ilen / reg_tuple_size); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		err = of_address_to_resource(np, i, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			pr_err("icp_native: Could not translate ICP MMIO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			       " for interrupt server 0x%x (%d)\n", *indx, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		if (icp_native_map_one_cpu(*indx, r.start, resource_size(&r)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		(*indx)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct icp_ops icp_native_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.get_irq	= icp_native_get_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.eoi		= icp_native_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.set_priority	= icp_native_set_cpu_priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.teardown_cpu	= icp_native_teardown_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.flush_ipi	= icp_native_flush_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.ipi_action	= icp_native_ipi_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.cause_ipi	= icp_native_cause_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int __init icp_native_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	u32 indx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	for_each_compatible_node(np, NULL, "ibm,ppc-xicp")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		if (icp_native_init_one_node(np, &indx) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		for_each_node_by_type(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			"PowerPC-External-Interrupt-Presentation") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				if (icp_native_init_one_node(np, &indx) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 					found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (found == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	icp_ops = &icp_native_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }