Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Common routines for Tundra Semiconductor TSI108 host bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * 2004-2005 (c) Tundra Semiconductor Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Alex Bounine (alexandreb@tundra.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Roy Zang (tie-fei.zang@freescale.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 	   Add pci interrupt router host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/tsi108.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/tsi108_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/tsi108_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DBG(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DBG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define tsi_mk_config_addr(bus, devfunc, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) u32 tsi108_pci_cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static u32 tsi108_pci_cfg_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) u32 tsi108_csr_vir_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static struct irq_domain *pci_irq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) extern u32 get_vir_csrbase(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) extern u32 tsi108_read_reg(u32 reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) extern void tsi108_write_reg(u32 reg_offset, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			   int offset, int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	volatile unsigned char *cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (ppc_md.pci_exclude_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 							devfunc, offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 							(offset & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	printk("PCI CFG write : ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	printk("data = 0x%08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		out_8((u8 *) cfg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		out_le16((u16 *) cfg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		out_le32((u32 *) cfg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) void tsi108_clear_pci_error(u32 pci_cfg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 err_stat, err_addr, pci_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * Quietly clear PB and PCI error flags set as result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * of PCI/X configuration read requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Read PB Error Log Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (err_stat & TSI108_PB_ERRCS_ES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/* Clear error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				 TSI108_PB_ERRCS_ES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		/* Clear read error reported in PB_ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				 TSI108_PB_ISR_PBS_RD_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		/* Clear PCI/X bus cfg errors if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		if ((err_addr & 0xFF000000) == pci_cfg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			pci_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 					 pci_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define __tsi108_read_pci_config(x, addr, op)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	__asm__ __volatile__(				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		"	"op" %0,0,%1\n"		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		"1:	eieio\n"			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		"2:\n"					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		".section .fixup,\"ax\"\n"		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		"3:	li %0,-1\n"			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		"	b 2b\n"				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		".previous\n"				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		EX_TABLE(1b, 3b)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		: "=r"(x) : "r"(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			  int len, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	volatile unsigned char *cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (ppc_md.pci_exclude_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 							devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 							offset) | (offset &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 								   0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	*val = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		printk("PCI CFG read : ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		printk("data = 0x%x\n", *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void tsi108_clear_pci_cfg_error(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tsi108_clear_pci_error(tsi108_pci_cfg_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct pci_ops tsi108_direct_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.read = tsi108_direct_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.write = tsi108_direct_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct resource rsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	const int *bus_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int has_address = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* PCI Config mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tsi108_pci_cfg_phys = cfg_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	    tsi108_pci_cfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Fetch host bridge registers address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Get bus range if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bus_range = of_get_property(dev, "bus-range", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (bus_range == NULL || len < 2 * sizeof(int)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		       " bus 0\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	hose = pcibios_alloc_controller(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (!hose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		printk("PCI Host bridge init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	hose->first_busno = bus_range ? bus_range[0] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	hose->last_busno = bus_range ? bus_range[1] : 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	(hose)->ops = &tsi108_direct_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	       "Firmware bus number: %d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	       rsrc.start, hose->first_busno, hose->last_busno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Interpret the "ranges" property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* This also maps the I/O region and sets isa_io/mem_base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	pci_process_bridge_OF_ranges(hose, dev, primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * Low level utility functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void tsi108_pci_int_mask(u_int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	u_int irp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int int_line = (irq - IRQ_PCI_INTAD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	irp_cfg |= (1 << int_line);	/* INTx_DIR = output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	irp_cfg &= ~(3 << (8 + (int_line * 2)));	/* INTx_TYPE = unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void tsi108_pci_int_unmask(u_int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u_int irp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int int_line = (irq - IRQ_PCI_INTAD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	irp_cfg &= ~(1 << int_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	irp_cfg |= (3 << (8 + (int_line * 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void init_pci_source(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			0x0000ff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			TSI108_PCI_IRP_ENABLE_P_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline unsigned int get_pci_source(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u_int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	u_int pci_irp_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	static int mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* Read PCI/X block interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* Process Interrupt from PCI bus INTA# - INTD# lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		temp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		    tsi108_read_reg(TSI108_PCI_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				    TSI108_PCI_IRP_INTAD) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		for (i = 0; i < 4; i++, mask++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			if (temp & (1 << mask % 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				irq = IRQ_PCI_INTA + mask % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				mask++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		/* Disable interrupts from PCI block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		pci_irp_stat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		temp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		temp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		printk("cfg_ctl=0x%08x ", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		temp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		printk("irp_enable=0x%08x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif	/* end of DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  * Linux descriptor level callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void tsi108_pci_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	tsi108_pci_int_unmask(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	/* Enable interrupts from PCI block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			 tsi108_read_reg(TSI108_PCI_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					 TSI108_PCI_IRP_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			 TSI108_PCI_IRP_ENABLE_P_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void tsi108_pci_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	tsi108_pci_int_mask(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void tsi108_pci_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	tsi108_pci_int_mask(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * Interrupt controller descriptor for cascaded PCI interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct irq_chip tsi108_pci_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.name = "tsi108_PCI_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.irq_mask = tsi108_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.irq_ack = tsi108_pci_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.irq_unmask = tsi108_pci_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int pci_irq_host_xlate(struct irq_domain *h, struct device_node *ct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			    const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			    irq_hw_number_t *out_hwirq, unsigned int *out_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	*out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	*out_flags = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int pci_irq_host_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			  irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if ((virq >= 1) && (virq <= 4)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		irq = virq + IRQ_PCI_INTAD_BASE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		irq_set_status_flags(irq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		irq_set_chip(irq, &tsi108_pci_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct irq_domain_ops pci_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.map = pci_irq_host_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.xlate = pci_irq_host_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)  * Exported functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)  * The Tsi108 PCI interrupts initialization routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)  * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  * PCI block has to be treated as a cascaded interrupt controller connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * to the MPIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void __init tsi108_pci_int_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	pci_irq_host = irq_domain_add_legacy_isa(node, &pci_irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (pci_irq_host == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		printk(KERN_ERR "pci_irq_host: failed to allocate irq domain!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	init_pci_source();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) void tsi108_irq_cascade(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	unsigned int cascade_irq = get_pci_source();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (cascade_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		generic_handle_irq(cascade_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	chip->irq_eoi(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }